公开(公告)号：US20170365658A1

公开(公告)日：2017-12-21

申请号：US15697522

申请日：2017-09-07

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Darsen D. Lu ,  Xin Miao ,  Tenko Yamashita

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.

公开(公告)号：US20170053943A1

公开(公告)日：2017-02-23

申请号：US15343387

申请日：2016-11-04

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/84 ,  H01L21/3065

CPC classification number: H01L27/1211 ,  H01L21/3065 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7849

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

Abstract translation: 一种制造半导体器件的方法，包括提供绝缘体上的应变硅（SSOI）结构，所述SSOI结构包括设置在衬底上的电介质层，设置在所述电介质层上的硅锗层和设置在所述绝缘体上的应变半导体材料层 直接在硅锗层上，在SSOI结构上形成多个鳍片，在nFET区域中的至少一个鳍片的一部分上形成栅极结构，在pFET区域中的至少一个鳍片的一部分上形成栅极结构 去除pFET区域中的至少一个鳍片的部分上的栅极结构，去除通过去除而暴露的硅锗层，并在pFET区域中的至少一个鳍片的部分上形成新的栅极结构， 新的门结构围绕四面的部分。

公开(公告)号：US20160204131A1

公开(公告)日：2016-07-14

申请号：US14595316

申请日：2015-01-13

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L21/3065 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/84 ,  H01L29/161

CPC classification number: H01L27/1211 ,  H01L21/3065 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7849

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

公开(公告)号：US20160197078A1

公开(公告)日：2016-07-07

申请号：US15069578

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/10 ,  H01L21/308 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

Abstract translation: 提供了包含通过外延半导体堆叠与下层体硅衬底隔离的半导体鳍片的非平面半导体结构。 提供隔离的外延半导体材料堆叠包括从底部到顶部的包含至少一种导电类型的不同于形成半导体鳍片的特定器件区域的导电类型的掺杂剂的半导体冲击穿通停止器，以及 不含n型或p型掺杂剂的半导体扩散阻挡层。

公开(公告)号：US20160197077A1

公开(公告)日：2016-07-07

申请号：US15069557

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

公开(公告)号：US09362400B1

公开(公告)日：2016-06-07

申请号：US14640382

申请日：2015-03-06

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A finFET semiconductor device includes a semiconductor-on-insulator (SOI) substrate including a buried insulator layer, a plurality of semiconductor fins on the buried insulator layer, and a gate structure covering the semiconductor fins, at least one buried stressor element embedded in the buried insulator layer, and a source/drain element on an upper surface of the at least one buried stressor element and integrally formed with at least one semiconductor fin among the plurality of semiconductor fins, the at least one buried stressor element applying a stress upon the source/drain element from therebeneath.

Abstract translation: 一种finFET半导体器件包括绝缘体上半导体（SOI）衬底，其包括掩埋绝缘体层，埋置绝缘体层上的多个半导体鳍片以及覆盖半导体鳍片的栅极结构，至少一个嵌入应力元件 埋入绝缘体层，以及在所述至少一个埋置的应力元件的上表面上的源极/漏极元件，并且与所述多个半导体鳍片中的至少一个半导体鳍片整体形成，所述至少一个埋置的应力元件在 源/漏元素。

公开(公告)号：US20160064210A1

公开(公告)日：2016-03-03

申请号：US14934191

申请日：2015-11-06

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L21/306

CPC classification number: H01L21/0251 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02664 ,  H01L21/2251 ,  H01L21/30604 ,  H01L21/7624 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of forming a semiconductor structure includes etching a semiconductor region of a substrate to form a thinned semiconductor region, and forming a silicon-germanium layer on the thinned semiconductor region, the silicon-germanium layer having a graded concentration profile of germanium atoms.

Abstract translation: 形成半导体结构的方法包括蚀刻衬底的半导体区域以形成变薄的半导体区域，并且在减薄的半导体区域上形成硅 - 锗层，所述硅 - 锗层具有锗原子的梯度浓度分布。

公开(公告)号：US20150364555A1

公开(公告)日：2015-12-17

申请号：US14835832

申请日：2015-08-26

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek

IPC: H01L29/36 ,  H01L27/12 ,  H01L29/16

CPC classification number: H01L21/0251 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02664 ,  H01L21/2251 ,  H01L21/30604 ,  H01L21/7624 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile.

公开(公告)号：US20150270344A1

公开(公告)日：2015-09-24

申请号：US14221339

申请日：2014-03-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek

IPC: H01L29/10 ,  H01L21/306 ,  H01L21/762 ,  H01L21/324 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L21/0251 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02664 ,  H01L21/2251 ,  H01L21/30604 ,  H01L21/7624 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile.

Abstract translation: 形成半导体结构的方法包括在具有特定锗原子浓度的衬底的半导体区域上形成硅 - 锗层。 半导体区域和硅锗层被退火以引起锗原子从硅 - 锗层到半导体区域的非均匀热扩散以形成梯度硅 - 锗区域。 形成半导体结构的另一种方法包括蚀刻衬底的半导体区域以形成变薄的半导体区域。 在具有分级锗浓度分布的变薄的半导体区域上形成硅 - 锗层。

公开(公告)号：US11728428B2

公开(公告)日：2023-08-15

申请号：US16682645

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Darsen D. Lu ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/306 ,  H01L21/324 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L21/02236 ,  H01L21/3086 ,  H01L21/30604 ,  H01L21/311 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.