公开(公告)号：US20200152622A1

公开(公告)日：2020-05-14

申请号：US16739754

申请日：2020-01-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Darsen D. Lu ,  Ghavam G. Shahidi

IPC: H01L27/06 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L23/522 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/94 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/08

Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.

公开(公告)号：US10347752B2

公开(公告)日：2019-07-09

申请号：US15866676

申请日：2018-01-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/32 ,  H01L21/324 ,  H01L29/10 ,  H01L29/161

Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.

公开(公告)号：US10177223B2

公开(公告)日：2019-01-08

申请号：US15697522

申请日：2017-09-07

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Darsen D. Lu ,  Xin Miao ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/283 ,  H01L29/417

Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.

公开(公告)号：US20180122944A1

公开(公告)日：2018-05-03

申请号：US15800740

申请日：2017-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Darsen D. Lu ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L29/7846 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

公开(公告)号：US20170125447A1

公开(公告)日：2017-05-04

申请号：US15407992

申请日：2017-01-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L21/324 ,  H01L21/84 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L21/32 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/18 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/785

Abstract: A method of forming a semiconductor structure that includes a tensily strained silicon fin extending upwards from a first portion of a substrate and in an nFET device region, and a SiGe fin structure extending upwards from a second portion of the substrate and in a pFET device region. In accordance with the present application, the SiGe fin structure comprises, from bottom to top, a lower SiGe fin that is relaxed and an upper SiGe fin, wherein the upper SiGe fin is compressively strained and has a germanium content that is greater than a germanium content of the lower SiGe fin.

公开(公告)号：US09564439B2

公开(公告)日：2017-02-07

申请号：US15069578

申请日：2016-03-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/10 ,  H01L21/308 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165

Abstract: A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

Abstract translation: 提供了包含通过外延半导体堆叠与下层体硅衬底隔离的半导体鳍片的非平面半导体结构。 提供隔离的外延半导体材料堆叠包括从底部到顶部的包含至少一种导电类型的不同于形成半导体鳍片的特定器件区域的导电类型的掺杂剂的半导体冲击穿通停止器，以及 不含n型或p型掺杂剂的半导体扩散阻挡层。

公开(公告)号：US20170005087A1

公开(公告)日：2017-01-05

申请号：US15235743

申请日：2016-08-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Darsen D. Lu ,  Ghavam G. Shahidi

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0629 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0924 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/94

Abstract: The electrical device includes a plurality of fin structures, the plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. Each of the plurality of fin structures having substantially a same geometry. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures, wherein the decoupling capacitor is present underlying the power line to the semiconductor fin structures.

Abstract translation: 电气装置包括多个翅片结构，所述多个翅片结构包括至少一个解耦翅片和至少一个半导体翅片。 多个翅片结构中的每一个具有基本上相同的几何形状。 电气装置包括至少一个半导体器件，其包括存在于至少一个半导体鳍片中的沟道区域，存在于至少一个半导体鳍片的沟道区域上的栅极结构以及存在于源极和漏极区域部分上的源极和漏极区域 的至少一个半导体鳍片。 电气装置包括至少一个去耦电容器，其包括作为去耦电容器的第一电极的去耦鳍结构，节点电介质层和由金属接触件提供到半导体鳍片结构的源极和漏极区域的第二电极，其中， 去耦电容器位于电力线下方到半导体鳍片结构。

公开(公告)号：US20160359003A1

公开(公告)日：2016-12-08

申请号：US15242992

申请日：2016-08-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L29/10 ,  H01L29/161 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/3065 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7849

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.

Abstract translation: 一种制造半导体器件的方法，包括提供绝缘体上的应变硅（SSOI）结构，所述SSOI结构包括设置在衬底上的电介质层，设置在所述电介质层上的硅锗层和设置在所述绝缘体上的应变半导体材料层 直接在硅锗层上，在SSOI结构上形成多个鳍片，在nFET区域中的至少一个鳍片的一部分上形成栅极结构，在pFET区域中的至少一个鳍片的一部分上形成栅极结构 去除pFET区域中的至少一个鳍片的部分上的栅极结构，去除通过去除而暴露的硅锗层，并在pFET区域中的至少一个鳍片的部分上形成新的栅极结构， 新的门结构围绕四面的部分。

公开(公告)号：US10593663B2

公开(公告)日：2020-03-17

申请号：US15235775

申请日：2016-08-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Darsen D. Lu ,  Ghavam G. Shahidi

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/66 ,  H01L23/528 ,  H01L27/092 ,  H01L29/78 ,  H01L49/02 ,  H01L23/522 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/94 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L23/485

Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.

公开(公告)号：US09966387B2

公开(公告)日：2018-05-08

申请号：US15343387

申请日：2016-11-04

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/3065 ,  H01L29/161 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/762 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/1211 ,  H01L21/3065 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7849

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.