公开(公告)号：US20180190901A1

公开(公告)日：2018-07-05

申请号：US15906480

申请日：2018-02-27

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Janusz J. Nowak ,  Eugene J. O'Sullivan

IPC: H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

公开(公告)号：US09960347B2

公开(公告)日：2018-05-01

申请号：US15499058

申请日：2017-04-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Janusz J. Nowak ,  Eugene J. O'Sullivan

IPC: H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

公开(公告)号：US09954063B2

公开(公告)日：2018-04-24

申请号：US15134190

申请日：2016-04-20

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/40 ,  H01L29/786 ,  H01L21/306

CPC classification number: H01L29/1037 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32134 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

公开(公告)号：US09859375B2

公开(公告)日：2018-01-02

申请号：US15134155

申请日：2016-04-20

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/40 ,  H01L29/786 ,  H01L21/306

CPC classification number: H01L29/1037 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32134 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

公开(公告)号：US20170222134A1

公开(公告)日：2017-08-03

申请号：US15493270

申请日：2017-04-21

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Nathan P. Marchack

IPC: H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode.

公开(公告)号：US09705077B2

公开(公告)日：2017-07-11

申请号：US14840176

申请日：2015-08-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Armand A. Galan ,  Steve Holmes ,  Eric A. Joseph ,  Gen P. Lauer ,  Qinghuang Lin ,  Nathan P. Marchack

IPC: H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  G03F7/70325 ,  G03F7/70425 ,  G11C11/161 ,  G11C2211/5615 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method for forming a memory device includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A planarizing layer is etched to establish a pillar of planarizing material defined by the island of photoresist material. A metal layer is etched to form a metal pillar having a diameter about the same as the pillar of planarizing material. A memory stack is etched to form a memory stack pillar having a diameter about the same as the metal pillar. A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.

公开(公告)号：US20170141299A1

公开(公告)日：2017-05-18

申请号：US14943247

申请日：2015-11-17

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Nathan P. Marchack ,  Stephen M. Rossnagel

IPC: H01L43/12

CPC classification number: H01L43/12

Abstract: A method of making a magnetic random access memory (MRAM) device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer positioned in contact with the electrode, a free layer, and a tunnel barrier layer arranged between the reference layer and the free layer; and depositing an encapsulating layer on and along sidewalls of the MTJ by physical sputtering or ablation of a target material onto the MTJ.

公开(公告)号：US09502640B1

公开(公告)日：2016-11-22

申请号：US14931141

申请日：2015-11-03

Applicant: International Business Machines Corporation

Inventor： Anthony J. Annunziata ,  Gen P. Lauer ,  Nathan P. Marchack

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode.

公开(公告)号：US09466673B2

公开(公告)日：2016-10-11

申请号：US15076871

申请日：2016-03-22

Applicant: International Business Machines Corporation

Inventor： Gen P. Lauer ,  Isaac Lauer ,  Alexander Reznicek ,  Jeffrey W. Sleight

IPC: H01L21/00 ,  H01L29/10 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/02 ,  H01L21/324 ,  H01L21/3065

CPC classification number: H01L29/1054 ,  G05B19/19 ,  G05B2219/45032 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/7849 ,  H01L29/785

Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.

公开(公告)号：US20160211327A1

公开(公告)日：2016-07-21

申请号：US15076871

申请日：2016-03-22

Applicant: International Business Machines Corporation

Inventor： Gen P. Lauer ,  Isaac Lauer ,  Alexander Reznicek ,  Jeffrey W. Sleight

IPC: H01L29/10 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/324 ,  H01L21/84 ,  H01L29/161

CPC classification number: H01L29/1054 ,  G05B19/19 ,  G05B2219/45032 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/7849 ,  H01L29/785

Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.