公开(公告)号：US09425108B1

公开(公告)日：2016-08-23

申请号：US14960378

申请日：2015-12-05

Applicant: International Business Machines Corporation

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/225 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/26506 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1116 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of exposed fin ends. A set of sidewall spacers are formed on the set of exposed fin ends, forming a set of spacer covered fin ends. The set of sidewall spacers prevent epitaxial growth at the set of spacer covered fin ends. A semiconductor device includes a set of fin structures having a set of fin ends. A set of inhibitory layers are disposed at the set of fin ends to inhibit excessive epitaxial growth at the fin ends.

Abstract translation: 描述了一种用于防止半导体器件中的外延生长的方法。 该方法包括切割FinFET结构的翅片以形成一组暴露的翅片末端。 一组侧壁间隔件形成在一组露出的翅片端部上，形成一组间隔件覆盖的翅片端部。 该侧壁间隔物组防止了在间隔物覆盖的翅片端部处的外延生长。 一种半导体器件包括具有一组翅片端部的翅片结构的集合。 一组抑制层设置在鳍片端部，以抑制翅片端部处的过度的外延生长。

公开(公告)号：US20150076498A1

公开(公告)日：2015-03-19

申请号：US14026172

申请日：2013-09-13

Applicant: Global Foundries, Inc. ,  International Business Machines Corporation

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L21/66

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

公开(公告)号：US10586855B2

公开(公告)日：2020-03-10

申请号：US15961264

申请日：2018-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/12

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US10396000B2

公开(公告)日：2019-08-27

申请号：US14789476

申请日：2015-07-01

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC: H01L21/66 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

公开(公告)号：US20180083124A1

公开(公告)日：2018-03-22

申请号：US15815616

申请日：2017-11-16

Applicant: International Business Machines Corporation

Inventor： Miaomiao Wang ,  Tenko Yamashita ,  Chun-chen Yeh ,  Hui Zang

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/66545

Abstract: In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into a substrate interfacing with the gate. The recess is filled at least partially with a first conductive material. The first conductive material is insulated from the gate. The fin is replaced with a replacement structure. The replacement structure is electrically connected to the first conductive material using a second conductive material. the second conductive material is insulated from a first surface of the finFET. A first electrical contact structure is fabricated on the first surface. A second electrical contact structure is fabricated on a second surface of the finFET, the second surface being on a different spatial plane than the first surface.

公开(公告)号：US09876089B2

公开(公告)日：2018-01-23

申请号：US15183390

申请日：2016-06-15

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Jin Cho ,  MiaoMiao Wang ,  Hui Zang

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/28 ,  H01L21/324 ,  H01L29/49

CPC classification number: H01L29/513 ,  H01L21/28026 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.

公开(公告)号：US20170162565A1

公开(公告)日：2017-06-08

申请号：US15179992

申请日：2016-06-11

Applicant: International Business Machines Corporation ,  GlobalFoundries,Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L27/088 ,  H01L29/16 ,  H01L29/06 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set of trenches from other fin structures. Each of the fin structures has a top surface which is higher than a top surface of a dielectric material in the set of trenches. A set of dielectric blocks is disposed at the set of fin ends, the dielectric blocks having a top surface level with or above the top surfaces of the fin structures which inhibit excessive epitaxial growth at the fin ends.

公开(公告)号：US20170025526A1

公开(公告)日：2017-01-26

申请号：US15183390

申请日：2016-06-15

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Jin Cho ,  MiaoMiao Wang ,  Hui Zang

IPC: H01L29/78 ,  H01L21/324 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28026 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.

Abstract translation: 实施例涉及一种形成鳍型场效应晶体管（FinFET）的部分的方法。 该方法包括形成至少一个翅片，并且在至少一个翅片的至少一部分上形成电介质层。 该方法还包括在电介质层的至少一部分上形成功函数层。 所述方法还包括形成与所述至少一个鳍片相邻的源极区域或漏极区域，以及执行退火操作，其中所述退火操作使所述电介质层和所述源极区域或所述漏极区域退火，并且其中所述功函数层提供 在退火操作期间到介电层的至少一部分的保护功能。

公开(公告)号：US20160365450A1

公开(公告)日：2016-12-15

申请号：US15208121

申请日：2016-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US20160365346A1

公开(公告)日：2016-12-15

申请号：US14735984

申请日：2015-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

Abstract translation: 一种形成用于半导体器件的栅极结构的方法，包括在存在于鳍状结构上的置换栅极结构的侧壁上形成第一间隔物，其中第一间隔物的上表面偏离替换栅极结构的上表面 并且在所述第一间隔物和所述替换栅极结构的所述暴露表面上形成至少第二间隔物。 该方法还可以包括用相邻的第一间隔件之间的第一空间中具有第一宽度部分的功能栅极结构代替替换栅极结构，以及在相邻的第二间隔物之间​​的第二空间中具有第二宽度的第二宽度部分，其中第二 宽度大于第一宽度。