公开(公告)号：US20150255528A1

公开(公告)日：2015-09-10

申请号：US14196137

申请日：2014-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Qizhi Liu

IPC: H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/76224 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53295 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.

Abstract translation: 在混合信号集成电路（IC）的体硅（Si）衬底中制造电介质区域的结构和方法提供了高Q无源谐振器。 通过湿法蚀刻在<100>方向内的本体Si衬底内的深沟槽扩大以形成连续的空腔，其由Si氧化物填充以形成电介质区域。 电介质区域增强了在混合信号IC的金属化层中形成的覆盖无源谐振器的质量（Q）。

公开(公告)号：US20150194416A1

公开(公告)日：2015-07-09

申请号：US14147186

申请日：2014-01-03

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  James S. Dunn ,  Blaine J. Gross ,  Qizhi Liu ,  James A. Slinkman

IPC: H01L27/02 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/3081 ,  H01L21/764 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7842

Abstract: Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.

Abstract translation: 各种实施例包括场效应晶体管（FET）以及形成这种FET的方法。 一种方法包括：在前体结构中形成第一组开口，其具有：具有晶体方向的硅衬底，所述硅衬底基本上与第一氧化物邻接; 覆盖硅衬底的硅锗（SiGe）层; 覆盖SiGe层的硅层; 覆盖硅层的第二氧化物; 以及覆盖所述第二氧化物的牺牲层，其中所述第一组开口各自暴露所述硅衬底; 底切在与硅衬底的晶体方向垂直的方向上蚀刻硅衬底以形成与第一组开口对应的沟槽; 钝化第一组开口中的SiGe层或硅层中的至少一个的暴露表面; 并且用电介质至少部分地填充每个沟槽。

公开(公告)号：US08857022B2

公开(公告)日：2014-10-14

申请号：US13686263

申请日：2012-11-27

Applicant: International Business Machines Corporation

Inventor： James S. Dunn ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC: H01G7/00 ,  H01G4/33 ,  H01G4/232 ,  H01L49/02 ,  H01G4/12 ,  H01L23/522 ,  H01G4/06 ,  H01L27/01

CPC classification number: H01G4/06 ,  H01G4/1209 ,  H01G4/232 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/016 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49156 ,  H01L2924/00

Abstract: A low capacitance density, high voltage MIM capacitor and the high density MIM capacitor and a method of manufacture are provided. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.

Abstract translation: 提供了低电容密度，高电压MIM电容器和高密度MIM电容器及其制造方法。 该方法包括沉积彼此交错的多个板和多个电介质层。 该方法还包括蚀刻多个板的最上面板的一部分，同时保护最上面的板的其它部分。 最上层的受保护的其它部分形成第一金属 - 绝缘体 - 金属（MIM）电容器的顶板，并且蚀刻暴露第二MIM电容器的顶板。

公开(公告)号：US20140209908A1

公开(公告)日：2014-07-31

申请号：US14242203

申请日：2014-04-01

Applicant: International Business Machines Corporation

Inventor： Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles S. Musante ,  BethAnn Rainey Lawrence ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L23/482 ,  H01L21/66

CPC classification number: H01L23/4825 ,  H01L21/6835 ,  H01L21/76819 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L29/1054 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/73251 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/804 ,  H01L2224/80487 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Abstract translation: 用于粘结衬底表面，键合衬底组件和用于键合衬底组件的设计结构的方法。 使用器件基板的第一表面形成产品芯片的器件结构。 在产品芯片上形成用于器件结构的互连结构的布线层。 布线层被平坦化。 临时处理晶片可移除地结合到平坦化的布线层。 响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面被结合到最终的手柄基板。 然后将临时手柄晶片从组件中取出。

公开(公告)号：US08722508B2

公开(公告)日：2014-05-13

申请号：US13832929

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

IPC: H01L21/764

CPC classification number: H01L21/76283 ,  H01L21/76289 ,  H01L27/0738 ,  H01L27/1203 ,  H01L29/0649

Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Abstract translation: 绝缘体上硅（SOI）衬底中的低谐波射频（RF）开关及其制造方法。 一种方法包括通过绝缘体层形成至少一个沟槽。 所述至少一个沟槽与形成在所述绝缘体层上的有源区域中的器件相邻。 该方法还包括在绝缘体层之下的衬底中形成至少一个空腔，并从该至少一个沟槽横向延伸到该器件的下方。