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公开(公告)号：US20230207611A1
公开(公告)日：2023-06-29
申请号：US18177613
申请日：2023-03-02
申请人： VueReal Inc.
发明人： Gholamreza Chaji , Ehsanollah Fathi
IPC分类号： H01L27/15 , H01L33/40 , H01L33/58 , H01L33/00 , H01L23/00 , H01L21/683 , H01L25/16 , H01L25/075
CPC分类号： H01L27/156 , H01L33/405 , H01L33/58 , H01L33/005 , H01L24/97 , H01L24/96 , H01L24/05 , H01L21/6835 , H01L24/13 , H01L24/24 , H01L25/167 , H01L24/92 , H01L25/0753 , H01L2933/0058 , H01L2933/0016 , H01L2224/96 , H01L2224/83002 , H01L2224/16227 , H01L2224/32225 , H01L2224/97 , H01L2224/83005 , H01L2224/32235 , H01L24/08 , H01L2224/24137 , H01L2224/83907 , H01L24/83 , H01L2224/81385 , H01L2224/80907 , H01L2224/16237 , H01L2224/80004 , H01L24/16 , H01L2224/08225 , H01L2224/80385 , H01L2224/04105 , H01L2224/12105 , H01L24/80 , H01L2224/92 , H01L24/32 , H01L2224/80006 , H01L2224/0401 , H01L2221/68322 , H01L2224/9202 , H01L2221/68354 , H01L2221/68363 , H01L2221/68381 , H01L2224/83385 , H01L33/44
摘要： This disclosure is related to post processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices. In another example, color conversion layers are integrated into the system substrate to create different output from the micro devices.
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公开(公告)号：US20170372925A1
公开(公告)日：2017-12-28
申请号：US15680706
申请日：2017-08-18
发明人： Hale Johnson , Gregory George , Aaron Loomis
IPC分类号： H01L21/67 , H01L21/687
CPC分类号： H01L21/67092 , H01L21/6719 , H01L21/67742 , H01L21/67748 , H01L21/6838 , H01L21/68707 , H01L21/68721 , H01L21/68728 , H01L21/68742 , H01L21/68771 , H01L24/08 , H01L24/75 , H01L24/80 , H01L24/94 , H01L2224/08145 , H01L2224/75101 , H01L2224/75251 , H01L2224/75252 , H01L2224/75301 , H01L2224/75305 , H01L2224/7531 , H01L2224/75312 , H01L2224/7565 , H01L2224/757 , H01L2224/75701 , H01L2224/75702 , H01L2224/75703 , H01L2224/75743 , H01L2224/75754 , H01L2224/80203 , H01L2224/80907 , H01L2224/94 , H01L2924/00012 , H01L2224/80 , H01L2924/00014
摘要： An industrial-scale system and method for handling precisely aligned and centered semiconductor substrate (e.g., wafer) pairs for substrate-to-substrate (e.g., wafer-to-wafer) aligning and bonding applications is provided. Some embodiments include an aligned substrate transport device having a frame member and a spacer assembly. The centered semiconductor substrate pairs may be positioned within a processing system using the aligned substrate transport device, optionally under robotic control. The centered semiconductor substrate pairs may be bonded together without the presence of the aligned substrate transport device in the bonding device. The bonding device may include a second spacer assembly which operates in concert with that of the aligned substrate transport device to perform a spacer hand-off between the substrates. A pin apparatus may be used to stake the substrates during the hand-off.
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公开(公告)号：US09640418B2
公开(公告)日：2017-05-02
申请号：US15150856
申请日：2016-05-10
发明人： Hale Johnson , Gregory George
IPC分类号： H01L21/67 , H01L21/677 , H01L21/687 , H01L21/683 , H01L23/00
CPC分类号： H01L21/67742 , H01L21/67092 , H01L21/6719 , H01L21/67748 , H01L21/6838 , H01L21/68707 , H01L21/68721 , H01L21/68742 , H01L24/08 , H01L24/75 , H01L24/80 , H01L24/83 , H01L24/94 , H01L2224/08145 , H01L2224/75101 , H01L2224/75251 , H01L2224/75252 , H01L2224/75301 , H01L2224/75305 , H01L2224/7531 , H01L2224/75312 , H01L2224/7565 , H01L2224/757 , H01L2224/75701 , H01L2224/75702 , H01L2224/75703 , H01L2224/75743 , H01L2224/75754 , H01L2224/80203 , H01L2224/80907 , H01L2224/94 , H01L2924/00012 , H01L2224/80 , H01L2924/00014
摘要： An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.
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公开(公告)号：US09536853B2
公开(公告)日：2017-01-03
申请号：US14543986
申请日：2014-11-18
发明人： Wei Lin , Leathen Shi , Spyridon Skordas , Kevin R. Winstel
CPC分类号： H01L24/32 , H01L21/187 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/80 , H01L24/83 , H01L24/94 , H01L33/0079 , H01L2224/03452 , H01L2224/03845 , H01L2224/04 , H01L2224/04026 , H01L2224/05073 , H01L2224/05082 , H01L2224/05187 , H01L2224/0519 , H01L2224/05687 , H01L2224/0569 , H01L2224/08145 , H01L2224/27452 , H01L2224/27616 , H01L2224/29023 , H01L2224/29083 , H01L2224/29187 , H01L2224/2919 , H01L2224/32145 , H01L2224/80 , H01L2224/80896 , H01L2224/80907 , H01L2224/80948 , H01L2224/81896 , H01L2224/83 , H01L2224/838 , H01L2224/83896 , H01L2224/83907 , H01L2224/83948 , H01L2224/94 , H01L2924/00012 , H01L2924/05442 , H01L2924/06 , H01L2924/0715 , H01L2924/3512 , H01L2924/35121 , H01L2924/00014
摘要： According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
摘要翻译： 根据本发明的至少一个实施例，晶片到晶片半导体器件包括具有形成在第一体基板层上的第一接合层的第一晶片衬底。 第二晶片衬底包括形成在第二块体衬底层上的第二结合层。 第二接合层结合到第一接合层以限定接合界面。 第一晶片衬底和第二晶片衬底中的至少一个包括被配置为增加接合界面的结合能的防裂膜层。
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5.发明申请SEMICONDUCTOR DEVICES HAVING STACKED STRUCTURES AND METHODS FOR FABRICATING THE SAME 有权具有堆叠结构的半导体器件及其制造方法公开(公告)号：US20160155724A1
公开(公告)日：2016-06-02
申请号：US14955124
申请日：2015-12-01
申请人： Taeyeong Kim , Byung Lyul Park , Seokho Kim , Pil-Kyu Kang , Hyoju Kim , Jin Ho An , Joo Hee Jang
发明人： Taeyeong Kim , Byung Lyul Park , Seokho Kim , Pil-Kyu Kang , Hyoju Kim , Jin Ho An , Joo Hee Jang
IPC分类号： H01L25/065 , H01L21/66 , H01L23/00 , H01L23/48 , H01L23/528
CPC分类号： H01L25/0657 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L22/32 , H01L23/3114 , H01L23/3128 , H01L23/3135 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/92 , H01L24/94 , H01L2221/68327 , H01L2224/03002 , H01L2224/03616 , H01L2224/0392 , H01L2224/04 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/08146 , H01L2224/09181 , H01L2224/13025 , H01L2224/131 , H01L2224/14515 , H01L2224/16146 , H01L2224/73251 , H01L2224/80201 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/80907 , H01L2224/92 , H01L2224/9222 , H01L2224/94 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06596 , H01L2924/15311 , H01L2924/3511 , H01L2224/80 , H01L2924/00014 , H01L2924/014 , H01L2224/11 , H01L2224/03 , H01L2224/81 , H01L2224/08 , H01L2224/16 , H01L2924/00012 , H01L22/00 , H01L21/304 , H01L2221/68304 , H01L2221/68381 , H01L21/78
摘要： Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other.
摘要翻译： 提供具有堆叠结构的半导体器件及其制造方法。 半导体器件包括至少一个单块，其包括堆叠在其上的第一半导体芯片和第二半导体芯片。 第一和第二半导体芯片中的每一个包括半导体衬底，该半导体衬底包括通孔，半导体衬底的前表面上的电路层和设置在电路层中并且与通孔电连接的前衬垫 。 半导体基板的表面彼此面对。 电路层彼此直接接触，使得半导体芯片彼此结合。
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公开(公告)号：US11735623B2
公开(公告)日：2023-08-22
申请号：US16912049
申请日：2020-06-25
申请人： VueReal Inc.
发明人： Gholamreza Chaji , Ehsanollah Fathi
IPC分类号： H01L27/15 , H01L33/40 , H01L33/58 , H01L33/00 , H01L23/00 , H01L21/683 , H01L25/16 , H01L25/075 , H01L33/44 , H01L33/62 , H01L33/60
CPC分类号： H01L27/156 , H01L21/6835 , H01L24/05 , H01L24/13 , H01L24/24 , H01L24/92 , H01L24/96 , H01L24/97 , H01L25/0753 , H01L25/167 , H01L33/005 , H01L33/405 , H01L33/58 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/80 , H01L24/83 , H01L33/44 , H01L33/60 , H01L33/62 , H01L2221/68322 , H01L2221/68354 , H01L2221/68363 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/08225 , H01L2224/12105 , H01L2224/16227 , H01L2224/16237 , H01L2224/24137 , H01L2224/32225 , H01L2224/32235 , H01L2224/80004 , H01L2224/80006 , H01L2224/80385 , H01L2224/80907 , H01L2224/81385 , H01L2224/83002 , H01L2224/83005 , H01L2224/83385 , H01L2224/83907 , H01L2224/92 , H01L2224/9202 , H01L2224/96 , H01L2224/97 , H01L2933/0016 , H01L2933/0058 , H01L2933/0066 , H01L2224/97 , H01L2224/80 , H01L2224/97 , H01L2224/83 , H01L2224/96 , H01L2224/80 , H01L2224/96 , H01L2224/83 , H01L2224/96 , H01L2224/82 , H01L2224/96 , H01L2224/11 , H01L2224/96 , H01L2224/03 , H01L2224/92 , H01L2224/80 , H01L21/486
摘要： This disclosure is related to post processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices. In another example, color conversion layers are integrated into the system substrate to create different output from the micro devices.
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公开(公告)号：US09806057B2
公开(公告)日：2017-10-31
申请号：US14643831
申请日：2015-03-10
申请人： DISCO CORPORATION
发明人： Kazuma Sekiya
IPC分类号： H01L21/00 , H01L23/00 , H01L21/683
CPC分类号： H01L24/97 , H01L21/6835 , H01L24/08 , H01L24/19 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/95 , H01L2221/68359 , H01L2221/68368 , H01L2224/08225 , H01L2224/26175 , H01L2224/27013 , H01L2224/27334 , H01L2224/29194 , H01L2224/32225 , H01L2224/80143 , H01L2224/80385 , H01L2224/80904 , H01L2224/80907 , H01L2224/83002 , H01L2224/83143 , H01L2224/83192 , H01L2224/83385 , H01L2224/8385 , H01L2224/83907 , H01L2224/9205 , H01L2224/95 , H01L2224/95146 , H01L2224/97 , H01L2924/12042 , H01L2924/00 , H01L2224/83 , H01L2224/80 , H01L2924/00014 , H01L2224/19
摘要： A chip arranging method for arranging a plurality of chips on a wafer includes a groove forming step of forming a plurality of intersecting grooves that mark off each of chip placement regions on the front surface side of the wafer, a liquid supplying step of supplying a liquid to the chip placement regions, a chip placing step of placing the chips on the liquid to position the chips in the chip placement regions by the surface tension of the liquid after carrying out the liquid supplying step, and a liquid removing step of removing the liquid to arrange the plurality of chips on the wafer after carrying out the chip placing step.
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公开(公告)号：US09653430B2
公开(公告)日：2017-05-16
申请号：US14955124
申请日：2015-12-01
申请人： Taeyeong Kim , Byung Lyul Park , Seokho Kim , Pil-Kyu Kang , Hyoju Kim , Jin Ho An , Joo Hee Jang
发明人： Taeyeong Kim , Byung Lyul Park , Seokho Kim , Pil-Kyu Kang , Hyoju Kim , Jin Ho An , Joo Hee Jang
IPC分类号： H01L25/065 , H01L21/66 , H01L23/00 , H01L23/48 , H01L23/528 , H01L23/31 , H01L21/683 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L22/32 , H01L23/3114 , H01L23/3128 , H01L23/3135 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/92 , H01L24/94 , H01L2221/68327 , H01L2224/03002 , H01L2224/03616 , H01L2224/0392 , H01L2224/04 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/08146 , H01L2224/09181 , H01L2224/13025 , H01L2224/131 , H01L2224/14515 , H01L2224/16146 , H01L2224/73251 , H01L2224/80201 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/80907 , H01L2224/92 , H01L2224/9222 , H01L2224/94 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06596 , H01L2924/15311 , H01L2924/3511 , H01L2224/80 , H01L2924/00014 , H01L2924/014 , H01L2224/11 , H01L2224/03 , H01L2224/81 , H01L2224/08 , H01L2224/16 , H01L2924/00012 , H01L22/00 , H01L21/304 , H01L2221/68304 , H01L2221/68381 , H01L21/78
摘要： Semiconductor devices having stacked structures and methods for fabricating the same are provided. A semiconductor device includes at least one single block including a first semiconductor chip and a second semiconductor chip stacked thereon. Each of the first and second semiconductor chips includes a semiconductor substrate including a through-electrode, a circuit layer on a front surface of the semiconductor substrate, and a front pad that is provided in the circuit layer and is electrically connected to the through-electrode. The surfaces of the semiconductor substrates face each other. The circuit layers directly contact each other such that the semiconductor chips are bonded to each other.
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公开(公告)号：US20160358881A1
公开(公告)日：2016-12-08
申请号：US14917318
申请日：2014-12-18
发明人： Andreas FEHKUHRER
IPC分类号： H01L23/00 , B32B37/00 , H01L21/683 , B32B38/18 , H01L23/544 , H01L25/00
CPC分类号： H01L24/80 , B32B37/0046 , B32B38/1841 , B32B38/1858 , B32B2309/105 , B32B2457/14 , H01L21/187 , H01L21/304 , H01L21/67092 , H01L21/6831 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/544 , H01L24/08 , H01L24/74 , H01L24/75 , H01L24/94 , H01L24/95 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68363 , H01L2221/68368 , H01L2221/68381 , H01L2223/54426 , H01L2223/54453 , H01L2224/0224 , H01L2224/0381 , H01L2224/0382 , H01L2224/03831 , H01L2224/0384 , H01L2224/08121 , H01L2224/08145 , H01L2224/74 , H01L2224/75251 , H01L2224/75272 , H01L2224/75701 , H01L2224/75702 , H01L2224/75704 , H01L2224/75705 , H01L2224/75724 , H01L2224/75725 , H01L2224/75734 , H01L2224/75735 , H01L2224/75744 , H01L2224/75745 , H01L2224/7598 , H01L2224/80 , H01L2224/80003 , H01L2224/80006 , H01L2224/8001 , H01L2224/80011 , H01L2224/8002 , H01L2224/80047 , H01L2224/80051 , H01L2224/80093 , H01L2224/80099 , H01L2224/8013 , H01L2224/80132 , H01L2224/80201 , H01L2224/80203 , H01L2224/80209 , H01L2224/80213 , H01L2224/80801 , H01L2224/80894 , H01L2224/80907 , H01L2224/92 , H01L2224/94 , H01L2224/95 , H01L2224/97 , H01L2225/06565 , H01L2924/00014 , H01L2924/00012 , H01L2221/68304
摘要： A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.
摘要翻译： 一种用于将第一衬底与第二衬底结合的方法，其特征在于，在所述接合之前所述第一衬底和/或所述第二衬底被薄化。
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公开(公告)号：US20160111394A1
公开(公告)日：2016-04-21
申请号：US14976484
申请日：2015-12-21
IPC分类号： H01L23/00 , H01L21/762 , H01L21/18
CPC分类号： H01L24/83 , H01L21/187 , H01L21/2007 , H01L21/70 , H01L21/76251 , H01L24/80 , H01L2224/80907 , H01L2224/83009 , H01L2224/83894 , H01L2224/83907 , H01L2924/01001 , H01L2924/01007 , H01L2924/01008 , H01L2924/01018 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106
摘要： A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate according to the following steps: forming a reservoir in a surface layer on the first contact surface, at least partially filling the reservoir with a first educt or a first group of educts, contacting the first contact surface with the second contact surface for formation of a prebond connection, and forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt with a second educt contained in a reaction layer of the second substrate.
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