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公开(公告)号:US10811305B2
公开(公告)日:2020-10-20
申请号:US15272758
申请日:2016-09-22
IPC分类号: H01L21/762 , H01L21/84 , H01L21/86 , H01L29/20 , H01L29/16 , H01L27/12 , H01L23/29 , H01L23/00 , H01L21/18 , H01L27/092 , H01L27/06 , H01L21/8258
摘要: A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer.
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公开(公告)号:US20170154783A1
公开(公告)日:2017-06-01
申请号:US15430722
申请日:2017-02-13
发明人: Cheng-Wei Cheng , Ning Li , Devendra K. Sadana , Leathen Shi , Kuen-Ting Shiu
IPC分类号: H01L21/306 , H01L21/02 , H01L21/027 , H01L21/67 , H01L21/683 , H01L29/20
CPC分类号: H01L21/30617 , H01L21/02395 , H01L21/02463 , H01L21/02488 , H01L21/02538 , H01L21/02546 , H01L21/0262 , H01L21/02664 , H01L21/0273 , H01L21/30612 , H01L21/67086 , H01L21/6835 , H01L21/6836 , H01L21/7813 , H01L29/20 , H01L29/201 , H01L2221/6835 , H01L2221/68368 , H01L2221/68381
摘要: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.
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公开(公告)号:US10211178B2
公开(公告)日:2019-02-19
申请号:US15491329
申请日:2017-04-19
发明人: Wei Lin , Leathen Shi , Spyridon Skordas , Kevin R. Winstel
IPC分类号: H01L21/18 , H01L23/00 , H01L33/00 , H01L21/762
摘要: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
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公开(公告)号:US10020279B2
公开(公告)日:2018-07-10
申请号:US15209269
申请日:2016-07-13
发明人: Wei Lin , Leathen Shi , Spyridon Skordas , Kevin R. Winstel
CPC分类号: H01L24/32 , H01L21/187 , H01L21/76251 , H01L21/76254 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/80 , H01L24/83 , H01L24/94 , H01L33/0079 , H01L2224/03452 , H01L2224/03845 , H01L2224/04 , H01L2224/04026 , H01L2224/05073 , H01L2224/05082 , H01L2224/05187 , H01L2224/0519 , H01L2224/05687 , H01L2224/0569 , H01L2224/08145 , H01L2224/27452 , H01L2224/27616 , H01L2224/29023 , H01L2224/29083 , H01L2224/29187 , H01L2224/32145 , H01L2224/80896 , H01L2224/80907 , H01L2224/80948 , H01L2224/81896 , H01L2224/83 , H01L2224/838 , H01L2224/83896 , H01L2224/83907 , H01L2224/83948 , H01L2224/94 , H01L2924/05442 , H01L2924/06 , H01L2924/0715 , H01L2924/3512 , H01L2924/35121 , Y02P80/30 , H01L2224/80 , H01L2924/00012 , H01L2924/00014
摘要: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
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公开(公告)号:US20170062232A1
公开(公告)日:2017-03-02
申请号:US14839755
申请日:2015-08-28
发明人: Cheng-Wei Cheng , Ning Li , Devendra K. Sadana , Leathen Shi , Kuen-Ting Shiu
IPC分类号: H01L21/306 , H01L29/201 , H01L21/02
CPC分类号: H01L21/30617 , H01L21/02395 , H01L21/02463 , H01L21/02488 , H01L21/02538 , H01L21/02546 , H01L21/0262 , H01L21/02664 , H01L21/0273 , H01L21/30612 , H01L21/67086 , H01L21/6835 , H01L21/6836 , H01L21/7813 , H01L29/20 , H01L29/201 , H01L2221/6835 , H01L2221/68368 , H01L2221/68381
摘要: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.
摘要翻译: 提出了一种执行外延剥离的方法,允许重新使用III-V衬底来生长III-V器件。 接收的样品包括具有顶表面的生长衬底,在顶表面上的牺牲层以及牺牲层上的器件层。 该衬底被支撑在容器内部,并且容器中充满湿蚀刻剂,使得湿蚀刻剂逐渐地蚀刻掉牺牲层并且器件层远离生长衬底。 在用湿蚀刻剂填充容器的同时,将样品支撑在容器中,使得生长衬底的顶表面与湿蚀刻剂的最上表面不平行。 以这种方式进行,剥离过程需要几乎没有样品的单独设置,并且能够进行批处理和高产量。
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公开(公告)号:US09865469B2
公开(公告)日:2018-01-09
申请号:US15430722
申请日:2017-02-13
发明人: Cheng-Wei Cheng , Ning Li , Devendra K. Sadana , Leathen Shi , Kuen-Ting Shiu
IPC分类号: H01L21/306 , H01L21/02 , H01L29/201 , H01L21/78 , H01L21/67 , H01L21/027 , H01L21/683 , H01L29/20
CPC分类号: H01L21/30617 , H01L21/02395 , H01L21/02463 , H01L21/02488 , H01L21/02538 , H01L21/02546 , H01L21/0262 , H01L21/02664 , H01L21/0273 , H01L21/30612 , H01L21/67086 , H01L21/6835 , H01L21/6836 , H01L21/7813 , H01L29/20 , H01L29/201 , H01L2221/6835 , H01L2221/68368 , H01L2221/68381
摘要: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.
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7.
公开(公告)号:US09536853B2
公开(公告)日:2017-01-03
申请号:US14543986
申请日:2014-11-18
发明人: Wei Lin , Leathen Shi , Spyridon Skordas , Kevin R. Winstel
CPC分类号: H01L24/32 , H01L21/187 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/80 , H01L24/83 , H01L24/94 , H01L33/0079 , H01L2224/03452 , H01L2224/03845 , H01L2224/04 , H01L2224/04026 , H01L2224/05073 , H01L2224/05082 , H01L2224/05187 , H01L2224/0519 , H01L2224/05687 , H01L2224/0569 , H01L2224/08145 , H01L2224/27452 , H01L2224/27616 , H01L2224/29023 , H01L2224/29083 , H01L2224/29187 , H01L2224/2919 , H01L2224/32145 , H01L2224/80 , H01L2224/80896 , H01L2224/80907 , H01L2224/80948 , H01L2224/81896 , H01L2224/83 , H01L2224/838 , H01L2224/83896 , H01L2224/83907 , H01L2224/83948 , H01L2224/94 , H01L2924/00012 , H01L2924/05442 , H01L2924/06 , H01L2924/0715 , H01L2924/3512 , H01L2924/35121 , H01L2924/00014
摘要: According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
摘要翻译: 根据本发明的至少一个实施例,晶片到晶片半导体器件包括具有形成在第一体基板层上的第一接合层的第一晶片衬底。 第二晶片衬底包括形成在第二块体衬底层上的第二结合层。 第二接合层结合到第一接合层以限定接合界面。 第一晶片衬底和第二晶片衬底中的至少一个包括被配置为增加接合界面的结合能的防裂膜层。
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公开(公告)号:US20170221850A1
公开(公告)日:2017-08-03
申请号:US15491329
申请日:2017-04-19
发明人: Wei Lin , Leathen Shi , Spyridon Skordas , Kevin R. Winstel
IPC分类号: H01L23/00
CPC分类号: H01L24/32 , H01L21/187 , H01L21/76251 , H01L21/76254 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/80 , H01L24/83 , H01L24/94 , H01L33/0079 , H01L2224/03452 , H01L2224/03845 , H01L2224/04 , H01L2224/04026 , H01L2224/05073 , H01L2224/05082 , H01L2224/05187 , H01L2224/0519 , H01L2224/05687 , H01L2224/0569 , H01L2224/08145 , H01L2224/27452 , H01L2224/27616 , H01L2224/29023 , H01L2224/29083 , H01L2224/29187 , H01L2224/32145 , H01L2224/80896 , H01L2224/80907 , H01L2224/80948 , H01L2224/81896 , H01L2224/83 , H01L2224/838 , H01L2224/83896 , H01L2224/83907 , H01L2224/83948 , H01L2224/94 , H01L2924/05442 , H01L2924/06 , H01L2924/0715 , H01L2924/3512 , H01L2924/35121 , Y02P80/30 , H01L2224/80 , H01L2924/00012 , H01L2924/00014
摘要: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.
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公开(公告)号:US09653308B2
公开(公告)日:2017-05-16
申请号:US14839755
申请日:2015-08-28
发明人: Cheng-Wei Cheng , Ning Li , Devendra K. Sadana , Leathen Shi , Kuen-Ting Shiu
IPC分类号: H01L21/306 , H01L21/02 , H01L29/201
CPC分类号: H01L21/30617 , H01L21/02395 , H01L21/02463 , H01L21/02488 , H01L21/02538 , H01L21/02546 , H01L21/0262 , H01L21/02664 , H01L21/0273 , H01L21/30612 , H01L21/67086 , H01L21/6835 , H01L21/6836 , H01L21/7813 , H01L29/20 , H01L29/201 , H01L2221/6835 , H01L2221/68368 , H01L2221/68381
摘要: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.
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10.
公开(公告)号:US20140166983A1
公开(公告)日:2014-06-19
申请号:US14010060
申请日:2013-08-26
发明人: Guy Cohen , Michael A. Guillorn , Alfred Grill , Leathen Shi
IPC分类号: H01L29/775
CPC分类号: H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66484 , H01L29/785 , H01L29/78696 , Y10S977/762 , Y10S977/888 , Y10S977/938
摘要: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.
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