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公开(公告)号：US20180286478A1
公开(公告)日：2018-10-04
申请号：US15854638
申请日：2017-12-26
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Sandeep Guliani , Balaji Srinivasan , Kiran Pangal
CPC classification number: G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C29/70
Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.
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公开(公告)号：US20180196612A1
公开(公告)日：2018-07-12
申请号：US15860648
申请日：2018-01-02
Applicant: Intel Corporation
Inventor： Kiran Pangal , Ravi J. Kumar
IPC: G06F3/06 , G11C29/52 , G11C29/50 , G11C29/02 , G11C16/34 , G11C16/26 , G11C16/14 , G11C11/56 , G06F11/20 , G06F11/10 , G11C16/00 , G11C29/04
CPC classification number: G06F3/0616 , G06F3/064 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G06F11/2094 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/14 , G11C16/26 , G11C16/3436 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/50016 , G11C29/52 , G11C2029/0401
Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20170186486A1
公开(公告)日：2017-06-29
申请号：US15333096
申请日：2016-10-24
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Sandeep Guliani , Balaji Srinivasan , Kiran Pangal
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C29/70
Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.
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公开(公告)号：US09685204B2
公开(公告)日：2017-06-20
申请号：US15189314
申请日：2016-06-22
Applicant: Intel Corporation
Inventor： Mase J Taub , Sandeep K. Guliani , Kiran Pangal
CPC classification number: G11C13/0004 , G11C5/02 , G11C7/00 , G11C13/004 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092 , G11C2213/77
Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.
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公开(公告)号：US09613691B2
公开(公告)日：2017-04-04
申请号：US14671972
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Davide Mantegazza , Prashant S. Damle , Kiran Pangal , Hanmant P. Belgal , Abhinav Pandey
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C2013/0052 , G11C2013/0057 , G11C2013/0083
Abstract: An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.
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Patent Agency Ranking
公开(公告)号：US09601193B1
公开(公告)日：2017-03-21
申请号：US14853246
申请日：2015-09-14
Applicant: Intel Corporation
Inventor： Raymond W. Zeng , Mase J. Taub , Kiran Pangal , Sandeep K. Guliani
IPC: G11C13/00
CPC classification number: G11C13/0028 , G11C8/06 , G11C13/0004 , G11C13/0021 , G11C13/0023 , G11C13/0026 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C16/08 , G11C16/3418 , G11C2013/0092
Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.
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公开(公告)号：US09543004B1
公开(公告)日：2017-01-10
申请号：US14742316
申请日：2015-06-17
Applicant: Intel Corporation
Inventor： Dany-Sebastien Ly-Gagnon , Kiran Pangal , Raymond W. Zeng , Mase J. Taub
CPC classification number: G11C11/00 , G06F11/1048 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2013/0092 , G11C2213/77 , H01L29/06 , H04L65/403
Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例描述了用于控制非易失性随机存取存储器（NVRAM）设备中的电流的技术和配置。 在一个实施例中，NVRAM器件可以包括耦合到多个位线的多个存储器单元，其形成具有寄生电容的位线节点。 每个存储器单元可以包括具有保持电流的所需电平的开关器件，以保持电池的导通状态。 电压供应电路和控制器可以与NVRAM器件耦合。 控制器可以控制电路以提供使存储器单元处于导通状态的电流脉冲。 响应于在实现设定点之后通过存储器单元的位线节点电容的放电，脉冲可以包括随时间从设定点改变到保持电流电平的分布。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09224465B2
公开(公告)日：2015-12-29
申请号：US14221572
申请日：2014-03-21
Applicant: Intel Corporation
Inventor： Nathan R. Franklin , Sandeep K. Guliani , Mase J. Taub , Kiran Pangal
CPC classification number: G11C13/004 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C2213/76
Abstract: The present disclosure relates to a cross-point memory bias scheme. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller configured to initiate selection of a target memory cell; a sense module configured to determine whether the target memory cell has been selected; and a C-cell bias module configured to establish a C-cell bias if the target cell is not selected.
Abstract translation: 本公开涉及一种交叉点存储器偏置方案。 一种装置，包括：存储器控制器，包括字线（WL）控制模块和位线控制模块，所述存储器控制器被配置为启动目标存储器单元的选择; 感测模块，其被配置为确定所述目标存储器单元是否已被选择; 以及配置为如果所述目标单元未被选择则建立C单元偏压的C单元偏置模块。
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公开(公告)号：US09153320B2
公开(公告)日：2015-10-06
申请号：US14028938
申请日：2013-09-17
Applicant: Intel Corporation
Inventor： Nathan R Franklin , Kiran Pangal
CPC classification number: G11C13/0069 , G11C11/24 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0045 , G11C2013/0076 , G11C2013/0078 , G11C2013/009 , G11C2013/0092 , G11C2207/063
Abstract: Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.
Abstract translation: 这里描述了与通过使用编程脉冲对存储器单元编程的一个或多个系统，装置，方法等相关的技术。
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公开(公告)号：US12230346B2
公开(公告)日：2025-02-18
申请号：US17358421
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Hemant P. Rao , Raymond W. Zeng , Prashant S. Damle , Zion S. Kwok , Kiran Pangal , Mase J. Taub
Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.
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