公开(公告)号：US11929396B2

公开(公告)日：2024-03-12

申请号：US17725471

申请日：2022-04-20

Applicant: INTEL CORPORATION

Inventor： William Hsu ,  Biswajeet Guha ,  Leonard Guler ,  Souvik Chakrabarty ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  B82Y10/00

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

公开(公告)号：US11894368B2

公开(公告)日：2024-02-06

申请号：US16727355

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/775 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.

公开(公告)号：US11869987B2

公开(公告)日：2024-01-09

申请号：US17860056

申请日：2022-07-07

Applicant: Intel Corporation

Inventor： Ayan Kar ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Kalyan Kolluru ,  Biswajeet Guha ,  Chung-Hsun Lin ,  Brian Greene ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/93 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/93 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/66174

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US20240008285A1

公开(公告)日：2024-01-04

申请号：US17856877

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Anand Murthy ,  Wilfred Gomes ,  Tahir Ghani

IPC: H01L27/11514 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/11514 ,  H01L29/0673 ,  H01L29/6684 ,  H01L29/78391

Abstract: Bits are stored in an array with multiple capacitors sharing a single access transistor and a common plate coupled to the transistor. A single common select transistor accesses information stored in an array of capacitors, above and below the transistor and sharing a common plate. The common plate may be vertical and encircled by each of the other plates. The capacitors may be ferroelectric capacitors. In an integrated circuit system, the array may be coupled to a power supply and a cooling structure.

公开(公告)号：US20240008244A1

公开(公告)日：2024-01-04

申请号：US17856879

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Sagar Suthram ,  Wilfred Gomes ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/108

CPC classification number: H01L27/108

Abstract: Bits are stored in cells having two transistors between two parallel bitlines. In a memory array, first and second transistor channels in a bit cell are parallel and offset and coupled to first and second bitlines, respectively, which are also parallel and offset. Adjacent bit cells share corresponding transistor channel structures. The transistor channels may be orthogonal to the bitlines. The memory array may be on an integrated circuit (IC) die, which may be coupled to a power supply in an IC system. In an IC system, the memory array may be coupled to a power supply and a cooling structure.

公开(公告)号：US20230422463A1

公开(公告)日：2023-12-28

申请号：US18312847

申请日：2023-05-05

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Kimberly L. Pierce ,  Elliot Tan ,  Pushkar Sharad Ranade ,  Shem Odhiambo Ogadhoh ,  Wilfred Gomes ,  Anand S. Murthy ,  Swaminathan Sivakumar ,  Tahir Ghani

IPC: H10B10/00

CPC classification number: H10B10/125

Abstract: SRAM devices with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to the edges of front or back faces of a support structure or a die on/in which the transistor resides, e.g., at an angle between about 10 and 80 degrees with respect to at least one of such edges. Implementing at least some of the transistors of SRAM cells as angled transistors may provide a promising way to increasing densities of SRAM cells on the limited real estate of semiconductor chips.

公开(公告)号：US20230420436A1

公开(公告)日：2023-12-28

申请号：US17846109

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L23/5226 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/08145

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface; a second region attached to the first region along a first planar interface that is orthogonal to the first surface; and a third region attached to the second region along a second planar interface that is parallel to the first planar interface, the third region having a second surface, the second surface being coplanar with the first surface. The first region and the third region comprise a plurality of layers of conductive traces in a dielectric material, the conductive traces being orthogonal to the first and second surfaces; and bond-pads on the first and second surfaces, the bond-pads comprising portions of the respective conductive traces exposed on the first and second surfaces.

公开(公告)号：US11843058B2

公开(公告)日：2023-12-12

申请号：US17516569

申请日：2021-11-01

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Abhishek Sharma ,  Van Le ,  Jack Kavalieros ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Tahir Ghani ,  Arnab Sen Gupta ,  Nazila Haratipour ,  Justin Weber

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/221

CPC classification number: H01L29/7869 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/221 ,  H01L29/78696

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

公开(公告)号：US11843054B2

公开(公告)日：2023-12-12

申请号：US16016381

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Van H. Le ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Miriam Reshotko ,  Matthew Metz ,  Yih Wang ,  Gilbert Dewey ,  Jack Kavalieros ,  Tahir Ghani ,  Nazila Haratipour ,  Abhishek Sharma ,  Shriram Shivaraman

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522 ,  H01L29/66 ,  H01L29/49 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L23/5226 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78645 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11837648B2

公开(公告)日：2023-12-05

申请号：US17695744

申请日：2022-03-15

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66439 ,  H01L27/1225 ,  H01L29/0669 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7869 ,  H01L29/78696

Abstract: Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.