公开(公告)号：US12176284B2

公开(公告)日：2024-12-24

申请号：US17398933

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Travis Lajoie ,  Abhishek Sharma ,  Juan Alzate-Vinasco ,  Chieh-Jen Ku ,  Shem Ogadhoh ,  Allen Gardiner ,  Blake Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L23/522 ,  H01L23/532 ,  H01L49/02 ,  H10B12/00

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US11997847B2

公开(公告)日：2024-05-28

申请号：US17588938

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Shriram Shivaraman ,  Yih Wang ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC classification number: H10B12/30 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78669 ,  H01L29/78693 ,  H10B12/05

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US11978804B2

公开(公告)日：2024-05-07

申请号：US17496690

申请日：2021-10-07

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Yih Wang

IPC: H01L29/786 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H10B12/00

CPC classification number: H01L29/78618 ,  H01L23/528 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78684 ,  H01L29/7869 ,  H01L29/78696 ,  H10B12/05 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

公开(公告)号：US11653487B2

公开(公告)日：2023-05-16

申请号：US16013798

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Yih Wang

IPC: H01L27/108 ,  H01L29/786

CPC classification number: H01L27/10802 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10897 ,  H01L29/78642

Abstract: Embodiments include a transistor device that comprises a gate electrode and a gate dielectric surrounding the gate electrode. In an embodiment, a source region may be below the gate electrode and a drain region may be above the gate electrode. In an embodiment, a channel region may be between the source region and the drain region. In an embodiment, the channel region is separated from a sidewall of the gate electrode by the gate dielectric. In an embodiment, a capacitor may be electrically coupled to the drain region.

公开(公告)号：US11329047B2

公开(公告)日：2022-05-10

申请号：US15956379

申请日：2018-04-18

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek A. Sharma ,  Tahir Ghani ,  Allen B. Gardiner ,  Travis W. Lajoie ,  Pei-hua Wang ,  Chieh-jen Ku ,  Bernhard Sell ,  Juan G. Alzate-Vinasco ,  Blake C. Lin

IPC: H01L27/108 ,  H01L27/12 ,  H01L23/528 ,  H01L23/522 ,  H01L27/06

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

公开(公告)号：US11114446B2

公开(公告)日：2021-09-07

申请号：US16349242

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Yih Wang

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/419 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  G11C11/417 ,  G11C7/18

Abstract: A memory device includes a first plurality of memory cells, a second plurality of memory cells, and a local sense amplifier between the first plurality of memory cells and the second plurality of memory cells, all on a first level, and a local bit line on a second level. The second level is vertically separated by one or more first inter-level dielectric layers from the first level in a first direction and the local bit line is electrically coupled to each memory cell of the first plurality of memory cells and the second plurality of memory cells, as well as the local sense amplifier. The memory device also includes a global bit line on a third level vertically separated by one or more inter-level dielectric layers from the first level in a second direction opposite the first direction, with the global bit line electrically coupled to the local sense amplifier.

公开(公告)号：US11031503B2

公开(公告)日：2021-06-08

申请号：US16329044

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Rafael Rios ,  Jack T. Kavalieros ,  Yih Wang ,  Shriram Shivaraman

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/50

Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.

公开(公告)号：US11024356B2

公开(公告)日：2021-06-01

申请号：US16565299

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC: G11C11/16 ,  G11C13/00 ,  G11C29/02

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US20200044095A1

公开(公告)日：2020-02-06

申请号：US16490503

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Sean Ma ,  Van H. Lee

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/108

Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).

公开(公告)号：US10483321B2

公开(公告)日：2019-11-19

申请号：US15575667

申请日：2015-06-02

Applicant: Intel Corporation

Inventor： Yih Wang ,  Patrick Morrow

IPC: H01L27/22 ,  H01L45/00 ,  H01L27/24 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  G11C13/00

Abstract: A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.