公开(公告)号：US08698516B2

公开(公告)日：2014-04-15

申请号：US13214144

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

IPC分类号： H03K17/16

CPC分类号： H03K19/17784 ,  H03K19/17792

摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

摘要翻译： 现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出所述at的至少一个电路的体偏值的范围 用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。 体偏置信号具有在体偏值范围内的值。

公开(公告)号：US20130043902A1

公开(公告)日：2013-02-21

申请号：US13214144

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Richard G. Cliff ,  Andy L. Lee ,  Ping-Chen Liu

IPC分类号： H03K19/177

CPC分类号： H03K19/17784 ,  H03K19/17792

摘要： A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

摘要翻译： 现场可编程门阵列（FPGA）包括一组监视器电路，其适于为FPGA中的至少一个电路提供过程，电压和温度的指示，以及控制器，其适于导出针对 用于至少一个电路的过程，电压和温度的指示的至少一个电路。 FPGA还包括体偏置发生器，其适于向至少一个电路中的至少一个晶体管提供体偏置信号。 体偏置信号具有在体偏值范围内的值。

公开(公告)号：US08369175B1

公开(公告)日：2013-02-05

申请号：US12874152

申请日：2010-09-01

申请人： Lin-Shih Liu ,  Andy L. Lee ,  Ping-Chen Liu ,  Irfan Rahim ,  Srinivas Perisetty

发明人： Lin-Shih Liu ,  Andy L. Lee ,  Ping-Chen Liu ,  Irfan Rahim ,  Srinivas Perisetty

IPC分类号： G11C5/14

CPC分类号： G11C11/412 ,  G11C15/04

摘要： Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.

摘要翻译： 集成电路可以包括具有电压过应力保护的存储器元件。 存储单元的一种合适布置可以包括具有两个交叉耦合的反相器的锁存器。 两个交叉耦合反相器中的每一个可以耦合在第一和第二电源线之间，并且可以包括具有连接到单独的电源线的栅极的晶体管。 另一种合适的存储单元布置可以包括三个交叉耦合电路。 三个电路中的两个可以由第一正电源线供电，而剩余电路可以由第二正电源线供电。 这些存储单元可用于向对应的通道提供升高的正静态控制信号和降低的地面静态控制信号。 这些存储单元可以包括在读/写操作期间使用的存取晶体管和读缓冲电路。

公开(公告)号：US08072237B1

公开(公告)日：2011-12-06

申请号：US12478713

申请日：2009-06-04

申请人： Irfan Rahim ,  Andy L. Lee

发明人： Irfan Rahim ,  Andy L. Lee

IPC分类号： G06F7/38 ,  H01L25/00

CPC分类号： H03K19/17784

摘要： Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different adjustable power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level. Memory elements associated with circuit blocks that contain critical paths can be overdriven at voltages that are larger than memory elements associated with circuit blocks that contain noncritical paths.

摘要翻译： 集成电路提供有诸如多路复用器的电路，其可以被选择性地配置为将不同的可调电源电压路由到集成电路上的不同电路块。 电路块可以包含由电源电压供电的存储器元件，并且以由电源电压确定的量值提供对应的静态输出控制信号。 来自存储元件的控制信号可以被施加到电路块中的晶体管的栅极。 集成电路上的逻辑可以在给定的电源电压电平下供电。 存储元件可以以相对于给定电源电压电平升高的过驱动电压电平提供其输出信号。 与包含关键路径的电路块相关联的存储器元件可以在大于与包含非关键路径的电路块相关联的存储器元件的电压上被过载。

公开(公告)号：US09455715B2

公开(公告)日：2016-09-27

申请号：US13174599

申请日：2011-06-30

申请人： Bruce B. Pedersen ,  Irfan Rahim

发明人： Bruce B. Pedersen ,  Irfan Rahim

IPC分类号： H03K19/177 ,  H03K19/00 ,  H03K19/003

CPC分类号： H03K19/17752 ,  H03K19/003

摘要： In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

摘要翻译： 在示例性实施例中，装置包括第一组电路元件和第二组电路元件。 第一组电路元件用于装置的第一配置，并且第二组电路元件用于装置的第二配置。 该设备的第一配置被切换到设备的第二配置，以便提高设备的可靠性。

公开(公告)号：US08643108B2

公开(公告)日：2014-02-04

申请号：US13214102

申请日：2011-08-19

申请人： Irfan Rahim ,  Jeffrey T. Watt ,  Yanzhong Xu ,  Lin-Shih Liu

发明人： Irfan Rahim ,  Jeffrey T. Watt ,  Yanzhong Xu ,  Lin-Shih Liu

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L21/761 ,  H01L29/66795

摘要： One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

摘要翻译： 一个实施例涉及缓冲晶体管器件。 该器件包括形成在半导体衬底中的缓冲的垂直鳍状结构。 垂直鳍状结构至少包括上半导体层，缓冲区和阱区​​的至少一部分。 缓冲区具有第一掺杂极性，并且阱区具有与第一掺杂极性相反的第二掺杂极性。 在缓冲区和阱区​​之间形成至少部分覆盖垂直鳍状结构的水平横截面的至少一个p-n结。 还公开了其它实施例，方面和特征。

公开(公告)号：US20080164936A1

公开(公告)日：2008-07-10

申请号：US12054382

申请日：2008-03-24

申请人： Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

发明人： Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

IPC分类号： G05F3/02 ,  H03K19/177

CPC分类号： H03K19/1731 ,  G06F17/5054 ,  H03K19/00369 ,  H03K2217/0018

摘要： A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

摘要翻译： 可编程逻辑器件（PLD）包括用于调整或设置一个或多个晶体管的体偏置的机构。 PLD包括体偏置发生器。 体偏置发生器被配置为设置可编程逻辑器件内的一个或多个晶体管的体偏置。 更具体地，体偏置发生器设置晶体管的体偏置，以便折衷晶体管的性能和功耗。

公开(公告)号：US07352610B1

公开(公告)日：2008-04-01

申请号：US11295815

申请日：2005-12-06

申请人： Bruce B. Pedersen ,  Irfan Rahim ,  Jeffrey T Watt

发明人： Bruce B. Pedersen ,  Irfan Rahim ,  Jeffrey T Watt

IPC分类号： G11C11/00

CPC分类号： G11C11/4125

摘要： Memory elements are provided that are immune to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements have nonlinear high-impedance two-terminal elements that restrict the flow of discharge currents during a particle strike. By lengthening the switching speed of the memory elements, the presence of the nonlinear high-impedance two-terminal elements prevents the states of the memory elements from flipping during discharge transients. The nonlinear high-impedance two-terminal elements may be formed from polysilicon p-n junction diodes, Schottky diodes, and other semiconductor structures. Data loading circuitry is provided to ensure that memory element arrays using the nonlinear high-impedance two-terminal elements can be loaded rapidly.

摘要翻译： 提供存储元件，当受到高能原子粒子撞击时，可以免受软错误不安事件的影响。 存储器元件具有非线性高阻抗二端元件，其限制了粒子撞击期间放电电流的流动。 通过延长存储元件的切换速度，非线性高阻抗二端元件的存在防止存储元件的状态在放电瞬变期间翻转。 非线性高阻抗二端元件可以由多晶硅p-n结二极管，肖特基二极管和其它半导体结构形成。 提供数据加载电路以确保使用非线性高阻抗二端元件的存储元件阵列可以快速加载。

公开(公告)号：US07183800B1

公开(公告)日：2007-02-27

申请号：US11302938

申请日：2005-12-14

申请人： Irfan Rahim ,  Jeffrey T. Watt

发明人： Irfan Rahim ,  Jeffrey T. Watt

IPC分类号： H03K19/173

CPC分类号： H03K19/0027 ,  H03K2217/0018

摘要： Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.

摘要翻译： 公开了用于改善可编程逻辑器件（PLD）的性能的装置和方法。 PLD包括被配置为分别向传输晶体管的栅极和传输晶体管的主体提供一对电压的存储单元。

公开(公告)号：US07170308B1

公开(公告)日：2007-01-30

申请号：US10628711

申请日：2003-07-28

申请人： Irfan Rahim ,  Peter McElheny ,  John Costello

发明人： Irfan Rahim ,  Peter McElheny ,  John Costello

IPC分类号： G01R31/00 ,  G01R31/28 ,  G05F1/00

CPC分类号： G11C5/147 ,  H03K19/177

摘要： The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted.

摘要翻译： 本发明通过使用对过程/产品参数的反馈来调节电路工作电压来优化集成电路的性能。 为了确定集成电路的工作电压的期望值，优选实施例提供一个或多个参考电路结构的片上探测，以测量一个或多个参考电路结构的至少一个电或操作参数; 基于所测量的参数确定所述工作电压的调整值; 并将调整后的值建立为工作电压的期望值。 参考电路结构可以包括在相同生产运行中制造的其它集成电路中的过程控制监视器结构或结构。 在替代实施例中，一个或多个参数是直接从其工作电压正被调整的集成电路测量的。