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    Register bus multiprocessor system with shift
    22.
    发明授权
    Register bus multiprocessor system with shift 失效
    寄存器总线多处理器系统

    公开(公告)号：US5119481A

    公开(公告)日：1992-06-02

    申请号：US696291

    申请日：1991-04-26

    申请人： Steven J. Frank ,  Henry Burkhardt, III ,  Frederick D. Weber

    发明人： Steven J. Frank ,  Henry Burkhardt, III ,  Frederick D. Weber

    IPC分类号： G06F15/173 ,  H04L12/433

    CPC分类号： H04L12/433 ,  G06F15/17337

    摘要： A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are connected in a ring configuration through the bus, with each cell being in communication with an associated subset of stages of the bus. At least one processing cell includes a cell interconnect that performs at least one of modifying, extracting, replicating and transferring a packet based on an association, if any, between a datum identified in that packet and one or more data stored in said associated memory element. The cell interconnect responds to applied digital clock cycle signals for simultaneously transferring at least a selected packet through successive stages of the bus at a rate responsive to the digital clock cycle rate, while performing the modifying, extracting, replicating and transferring operation.

    摘要翻译： 数字数据处理装置包括传送数字信息包的移位寄存器总线。 该总线具有以环形配置串联连接的多个数字存储和传送级。 每个包括至少一个存储器元件的多个处理单元通过总线以环形配置连接，每个单元与总线的相关分级子集通信。 至少一个处理单元包括单元互连，其执行基于在该分组中识别的数据与存储在所述相关联的存储器元件中的一个或多个数据之间的关联（如果有的话）修改，提取，复制和传送分组中的至少一个 。 小区互连响应所应用的数字时钟周期信号，用于在执行修改，提取，复制和传送操作的同时以响应于数字时钟周期速率的速率在总线的连续级中同时传送至少一个选定分组。

    General Purpose Digital Data Processor, Systems and Methods
    25.
    发明申请
    General Purpose Digital Data Processor, Systems and Methods 审中-公开
    通用数字数据处理器，系统和方法

    公开(公告)号：US20130086328A1

    公开(公告)日：2013-04-04

    申请号：US13495807

    申请日：2012-06-13

    申请人： Steven J. Frank ,  Hai Lin

    发明人： Steven J. Frank ,  Hai Lin

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0875 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/604

    摘要： The invention provides improved data processing apparatus, systems and methods that include one or more nodes, e.g., processor modules or otherwise, that include or are otherwise coupled to cache, physical or other memory (e.g., attached flash drives or other mounted storage devices) collectively, “system memory.” At least one of the nodes includes a cache memory system that stores data (and/or instructions) recently accessed (and/or expected to be accessed) by the respective node, along with tags specifying addresses and statuses (e.g., modified, reference count, etc.) for the respective data (and/or instructions). The tags facilitate translating system addresses to physical addresses, e.g., for purposes of moving data (and/or instructions) between system memory (and, specifically, for example, physical memory—such as attached drives or other mounted storage) and the cache memory system.

    摘要翻译： 本发明提供了改进的数据处理设备，系统和方法，其包括一个或多个节点，例如处理器模块或其他节点，其包括或者以其他方式耦合到高速缓存，物理或其他存储器（例如，附接的闪存驱动器或其他安装的存储设备） 统称为系统内存。 节点中的至少一个包括高速缓冲存储器系统，其存储由相应节点最近访问（和/或预期被访问）的数据（和/或指令）以及指定地址和状态的标签（例如，经修改的参考计数 等等）对于各自的数据（和/或指令）。 标签有助于将系统地址转换为物理地址，例如为了在系统存储器之间移动数据（和/或指令）的目的（特别是例如物理存储器，例如附接的驱动器或其它安装的存储器）和高速缓冲存储器 系统。

    Virtual processor methods and apparatus with unified event notification and consumer-produced memory operations
    26.
    发明授权
    Virtual processor methods and apparatus with unified event notification and consumer-produced memory operations 有权
    具有统一事件通知和消费者生成的内存操作的虚拟处理器方法和设备

    公开(公告)号：US08087034B2

    公开(公告)日：2011-12-27

    申请号：US12605839

    申请日：2009-10-26

    申请人： Steven J. Frank ,  Shigeki Imai ,  Terumasa Yoneda

    发明人： Steven J. Frank ,  Shigeki Imai ,  Terumasa Yoneda

    IPC分类号： G06F13/00

    CPC分类号： G06F9/3009 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3013 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/4812 ,  G06F9/542 ,  G06F2209/543 ,  Y02D10/24

    摘要： The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. An event delivery mechanism associates events with respective threads and notifies those threads when the events occur, regardless of which virtual processing unit and/or processor the threads happen to be executing on at the time. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing within such processor can execute a memory instruction (e.g., an “Empty” or other memory-consumer instruction) that permits the thread to wait on the availability of data generated, e.g., by another thread and to transparently wake up when that other thread makes the data available (e.g., by execution of a “Fill” or other memory-producer instruction).

    摘要翻译： 本发明在一个方面提供了一种包括一个或多个虚拟处理单元的虚拟处理器。 这些虚拟处理单元在一个或多个处理器上执行，并且每个虚拟处理单元执行一个或多个进程或线程（统称为“线程”）。 虽然线程可能被限制为在相同的虚拟处理单元上在其各自的寿命期间执行，但是它们不需要。 事件传递机制将事件与相应的线程相关联，并且在事件发生时通知这些线程，而不管线程何时正在执行的哪个虚拟处理单元和/或处理器。 本发明在其它方面提供具有改进的基于数据流的同步的虚拟和/或数字数据处理器。 在这种处理器内执行的过程或线程（统称为“线程”）可以执行允许线程等待生成的数据的可用性的存储器指令（例如，“空”或其他存储器 - 消费者指令），例如 ，另一个线程透明地唤醒，当另一个线程使数据可用时（例如，通过执行“填充”或其他存储器 - 生成器指令）。