公开(公告)号：US5821146A

公开(公告)日：1998-10-13

申请号：US479880

申请日：1995-06-07

申请人： Kuang-Yeh Chang ,  Yowjuang W. Liu ,  Mark I. Gardner ,  Fred Hause

发明人： Kuang-Yeh Chang ,  Yowjuang W. Liu ,  Mark I. Gardner ,  Fred Hause

IPC分类号： H01L21/266 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/336

CPC分类号： H01L21/266 ,  H01L21/823814 ,  H01L27/0925

摘要： A method of manufacturing a transistor having LDD regions in which the source and drain regions are formed by implanting ions through a photoresist layer at an energy of 1 MeV and greater and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate. In a second embodiment, the source and drain regions are formed without a photoresist layer by ion implantation and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate.

摘要翻译： 一种制造具有LDD区域的方法，其中通过以1MeV和更大的能量注入离子通过光致抗蚀剂层形成源极和漏极区域，并且在除去氧化物层之后通过低能离子注入形成LDD区域 从有源区和门。 在第二实施例中，源极和漏极区域通过离子注入形成为没有光致抗蚀剂层，并且在从有源区域和栅极去除氧化物层之后，通过低能离子注入形成LDD区域。

公开(公告)号：US5789298A

公开(公告)日：1998-08-04

申请号：US743643

申请日：1996-11-04

申请人： Mark I. Gardner ,  Fred Hause

发明人： Mark I. Gardner ,  Fred Hause

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66659 ,  H01L29/6656 ,  H01L29/7835

摘要： A method of fabricating a field effect transistor (FET) having an asymmetrical spacer formation includes the steps of forming a gate oxide and a gate electrode on a semiconductor material of a first conductivity type. The gate electrode includes a first and second side edges proximate first and second regions, respectively, of the semiconductor material. Ions of a second conductivity type are implanted to form lightly doped regions extending at least between the first side edge and the first region and at least between the second side edge and the second region, respectively. Blanket layers of oxide and nitride are then formed on the gate electrode and the semiconductor material. The nitride layer is patterned and a first sidewall spacer is formed in a remaining portion of the nitride layer proximate the second side edge. A second blanket layer of oxide is then formed on the first oxide layer and first sidewall spacer. Lastly, second sidewall spacers are formed in the second oxide layer, wherein a first one of the second sidewall spacers includes oxide of a first lateral dimension proximate the first side edge and wherein a second one of the second sidewall spacers is juxtaposed with the first sidewall spacer to form a composite sidewall spacer of a second lateral dimension greater than the first lateral dimension. A novel FET is disclosed also.

摘要翻译： 制造具有不对称间隔物形成的场效应晶体管（FET）的方法包括以下步骤：在第一导电类型的半导体材料上形成栅极氧化物和栅电极。 栅极电极包括分别靠近半导体材料的第一和第二区域的第一和第二侧边缘。 植入第二导电类型的离子以形成至少在第一侧边缘和第一区域之间以及至少在第二侧边缘和第二区域之间延伸的轻掺杂区域。 然后在栅电极和半导体材料上形成氧化物层和氮化物层。 图案化氮化物层，并且第一侧壁间隔物形成在靠近第二侧边缘的氮化物层的剩余部分中。 然后在第一氧化物层和第一侧壁间隔物上形成第二覆盖层氧化物。 最后，第二侧壁间隔物形成在第二氧化物层中，其中第二侧壁间隔物中的第一侧壁间隔物包括靠近第一侧边缘的第一侧向尺寸的氧化物，并且其中第二侧壁间隔物中的第二侧壁间隔物与第一侧壁并置 间隔件以形成大于第一横向尺寸的第二横向尺寸的复合侧壁间隔件。 还公开了一种新颖的FET。

公开(公告)号：US08564120B2

公开(公告)日：2013-10-22

申请号：US12642989

申请日：2009-12-21

申请人： Anthony Mowry ,  David Farber ,  Fred Hause ,  Markus Lenski

发明人： Anthony Mowry ,  David Farber ,  Fred Hause ,  Markus Lenski

IPC分类号： H01L23/36 ,  H01L21/00

CPC分类号： H01L23/427 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/522 ,  H01L27/16 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00

摘要： By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.

摘要翻译： 通过在半导体器件的温度关键区域中提供散热元件或热管，可以实现增强的性能，可靠性和封装密度。 散热元件可以基于标准制造技术形成，并且可以定位成紧靠各个晶体管元件和/或可用于屏蔽特定的电路部分。

公开(公告)号：US07804107B1

公开(公告)日：2010-09-28

申请号：US11906619

申请日：2007-10-03

申请人： Andrew E. Horch ,  Fred Hause

发明人： Andrew E. Horch ,  Fred Hause

IPC分类号： H01L31/111

CPC分类号： H01L21/84 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/1027 ,  H01L27/1203 ,  H01L29/66378

摘要： In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.

摘要翻译： 在半导体器件的处理方法中，可以在半导体材料上形成硅化物阻挡层。 在限定硅化物阻挡层之后，可以将杂质注入半导体材料的部分，如由硅化物阻挡层所限定的。 在植入之后，硅化物可以形成在半导体材料的表面区域，如硅化物阻挡层所允许的。 杂质植入物的区域可以包括与其上形成的硅化物的轮廓相关的边界。 在另一实施例中，植入物可以限定到晶闸管器件的基极区域。 可以以入射角来执行植入物，以将阻挡掩模的外围边缘下方的基底区域的部分延伸。 接下来，可以使用基本上正交的入射角并与掩模自对准的植入物形成阳极 - 发射极区域。 然后可以在由硅化物阻挡掩模限定的半导体材料的暴露区域上选择性地形成外延材料。 也可以在由硅化物阻挡掩模定义的选择的暴露区域之后形成硅化物。 硅化物阻挡掩模因此可用于植入物的对准，并且还用于限定外延和硅化物对准。

公开(公告)号：US07745337B2

公开(公告)日：2010-06-29

申请号：US12122840

申请日：2008-05-19

申请人： David G. Farber ,  Fred Hause ,  Markus Lenski ,  Anthony C. Mowry

发明人： David G. Farber ,  Fred Hause ,  Markus Lenski ,  Anthony C. Mowry

IPC分类号： H01L21/311

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L29/6653 ,  H01L29/78

摘要： A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.

摘要翻译： 一种方法，包括在衬底上形成半导体器件的栅极，并且蚀刻栅极侧面上的侧壁间隔物以提供接近值，其中接近值被定义为栅极与性能增强的边缘之间的距离 地区。 侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。 该方法还包括预先清洁栅极和基板以准备形成区域，其中在连续真空中进行蚀刻和预清洁。

公开(公告)号：US06967160B1

公开(公告)日：2005-11-22

申请号：US11042194

申请日：2005-01-26

申请人： Eric Paton ,  Paul Raymond Besser ,  Simon S. Chan ,  Fred Hause

发明人： Eric Paton ,  Paul Raymond Besser ,  Simon S. Chan ,  Fred Hause

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/28052 ,  H01L29/665 ,  H01L29/6659

摘要： Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.

摘要翻译： 通过在下面的硅和硅化镍层之间形成扩散转换层来实现具有显着降低的界面粗糙度的硅化镍形成。 实施例包括将氮离子注入到衬底和栅电极中，沉积钛或钽的薄层，沉积镍层，然后加热以形成在下硅和硅化镍层之间的界面处含有氮的扩散调制层。

公开(公告)号：US20050101120A1

公开(公告)日：2005-05-12

申请号：US10400212

申请日：2003-03-27

申请人： Fred Hause ,  Gert Burbach ,  Volker Kahlert

发明人： Fred Hause ,  Gert Burbach ,  Volker Kahlert

IPC分类号： H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76856

摘要： In a barrier formation process, an adhesion layer of refractory metal is deposited on sidewalls and bottom portions of a trench, and, subsequently, a nitride layer of the refractory metal is formed on the adhesion layer. After forming the nitride layer, the substrate is subjected to a heat treatment in a nitrogen-containing atmosphere to further convert residual refractory metal into nitride, thereby improving the barrier properties of the nitride layer in a subsequent process for filling in a contact metal, such as tungsten.

摘要翻译： 在阻挡层形成工艺中，将难熔金属的粘合层沉积在沟槽的侧壁和底部上，随后在粘合层上形成难熔金属的氮化物层。 在形成氮化物层之后，将基板在含氮气氛中进行热处理，以将残余难熔金属进一步转化为氮化物，从而在随后的填充接触金属的过程中改善氮化物层的阻挡性能， 作为钨。

公开(公告)号：US06888176B1

公开(公告)日：2005-05-03

申请号：US10609185

申请日：2003-06-26

申请人： Andrew E. Horch ,  Fred Hause

发明人： Andrew E. Horch ,  Fred Hause

IPC分类号： H01L21/332 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/66393 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41716 ,  H01L29/7436

摘要： In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.

摘要翻译： 在半导体器件的处理方法中，可以在半导体材料上形成硅化物阻挡层。 在限定硅化物阻挡层之后，可以将杂质注入半导体材料的部分，如由硅化物阻挡层所限定的。 在植入之后，硅化物可以形成在半导体材料的表面区域，如硅化物阻挡层所允许的。 杂质植入物的区域可以包括与其上形成的硅化物的轮廓相关的边界。 在另一实施例中，植入物可以限定到晶闸管器件的基极区域。 可以以入射角来执行植入物，以将阻挡掩模的外围边缘下方的基底区域的部分延伸。 接下来，可以使用基本上正交的入射角并与掩模自对准的植入物形成阳极 - 发射极区域。 然后可以在由硅化物阻挡掩模限定的半导体材料的暴露区域上选择性地形成外延材料。 也可以在由硅化物阻挡掩模定义的选择的暴露区域之后形成硅化物。 硅化物阻挡掩模因此可用于植入物的对准，并且还用于限定外延和硅化物对准。

公开(公告)号：US06242330B1

公开(公告)日：2001-06-05

申请号：US08994200

申请日：1997-12-19

申请人： Jon Cheek ,  Derick J. Wristers ,  Fred Hause

发明人： Jon Cheek ,  Derick J. Wristers ,  Fred Hause

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518

摘要： A process for breaking silicide stringers extending between silicide regions of different active regions on a semiconductor device is provided. Consistent with an exemplary fabrication process, two adjacent silicon active regions are formed on a substrate and a metal layer is formed over the two adjacent silicon active regions. The metal layer is then reacted with the silicon active regions to form a metal silicide on each silicon active region. This silicide reaction also forms silicide stringers extending from each silicon active region. Finally, at least part of each silicide stringer is removed. During the formation of the silicide stringers at least one silicide stringer may be formed which bridges the metal silicide over one of the silicon regions and the metal silicide over the other silicon region. In such circumstances, the removal process may, for example, break the silicide stringer and electrically decouple the two silicon regions. The two silicon active regions may, for example, be a gate electrode and an adjacet source/drain region. As another example, the two adjacent active regions may be two nearby polysilicon lines.

摘要翻译： 提供了一种用于在半导体器件上破坏在不同有源区的硅化物区之间延伸的硅化物桁条的工艺。 与示例性制造工艺一致，在衬底上形成两个相邻的硅有源区，并且在两个相邻的硅有源区上形成金属层。 然后金属层与硅有源区反应，以在每个硅有源区上形成金属硅化物。 这种硅化物反应也形成从每个硅活性区延伸的硅化物桁条。 最后，每个硅化物纵梁的至少部分被去除。 在硅化物桁条的形成期间，可以形成至少一个硅化物桁条，其将金属硅化物跨过其中一个硅区域和金属硅化物超过另一个硅区域。 在这种情况下，移除过程可能会例如破坏硅化物纵梁并使两个硅区域电耦合。 两个硅有源区可以例如是栅电极和辅助源/漏区。 作为另一示例，两个相邻的有源区可以是两个附近的多晶硅线。

公开(公告)号：US06054385A

公开(公告)日：2000-04-25

申请号：US792086

申请日：1997-01-31

申请人： Mark I. Gardner ,  Fred Hause

发明人： Mark I. Gardner ,  Fred Hause

IPC分类号： H01L21/768 ,  H01L21/283

CPC分类号： H01L21/76895

摘要： A semiconductor process in which a local interconnect, formed above a first transistor level, is connected to the first transistor level through a self-aligned and low resistivity contact structure. A semiconductor substrate is provided and a first transistor level formed on an upper surface of the semiconductor substrate. The first transistor level includes a first transistor. A local interconnect is then formed over the first transistor level. The local interconnect is vertically displaced above the first transistor level such that the local interconnect may traverse a gate of the first transistor without contacting the gate. A contact structure is then formed to connect the first source/drain structure of the first transistor with the local interconnect. The contact structure includes a first self-aligned silicide at an interface between the contact structure and the first source/drain region and further includes a second self-aligned silicide at an interface between the contact structure and the local interconnect.

摘要翻译： 形成在第一晶体管级上方的局部互连通过自对准和低电阻率接触结构连接到第一晶体管级的半导体工艺。 提供半导体衬底，并且形成在半导体衬底的上表面上的第一晶体管级。 第一晶体管电平包括第一晶体管。 然后在第一晶体管级上形成局部互连。 局部互连在第一晶体管电平之上垂直位移，使得局部互连可以穿过第一晶体管的栅极而不接触栅极。 然后形成接触结构以将第一晶体管的第一源极/漏极结构与局部互连连接。 接触结构包括在接触结构和第一源极/漏极区之间的界面处的第一自对准硅化物，并且还包括在接触结构和局部互连之间的界面处的第二自对准硅化物。