-
公开(公告)号：US6137129A
公开(公告)日：2000-10-24
申请号：US2825
申请日：1998-01-05
IPC分类号： H01L21/8244 , H01L27/11 , H01L27/108 , H01L29/74 , H01L29/76
CPC分类号： H01L27/11 , Y10S257/903
摘要： A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer. Second, the cell pass gates are formed on a pass gate or Input/Output (I/O) layer. Third, the I/O layer is bonded to and connected to the preferred latch layer.
摘要翻译： 一对直接耦合的场效应晶体管（FET），直接耦合FETS的锁存器，包括直接耦合FET的锁存器的静态随机存取存储器（SRAM）单元和形成直接耦合的FET结构的过程，锁存器和SRAM单元 。 可以是PFET，NFET或者其中之一的垂直FET是由栅极氧化物SiO 2分离的外延生长的NPN或PNP堆叠。 每个设备的门是该对的另一个设备的源或漏极。 优选实施例锁存器包括两对这样的直接耦合的垂直FET对，连接在一起以形成交叉耦合的反相器。 通路栅极层结合到优选实施例锁存器的一个表面上以形成优选实施例SRAM单元的阵列。 SRAM单元可以包括一个或两个传递门。 优选实施例SRAM过程具有三个主要步骤。 首先，优选实施例的锁存器形成在硅晶片上的氧化物层中。 第二，在传输门或输入/输出（I / O）层上形成单元传输门。 第三，I / O层被粘合并连接到优选的锁存层。
-
公开(公告)号：US5896404A
公开(公告)日：1999-04-20
申请号：US833371
申请日：1997-04-04
CPC分类号： G06F11/1008 , G11C7/1018 , G06F11/1052
摘要： A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is programmed in Normal mode, the burst length is 8 and the entire array address space is available for data storage. When the DRAM is programmed for error checking (ECC mode), the burst length is nine and the array is reconfigured with part of the array providing the ninth byte. The DRAM's address space is reduced by one-eighth in ECC mode. Preferably, all nine locations are in the same page, with each page being divided into eight equal portions. In Normal mode all eight equal portions are data storage; and, in ECC mode, seven-eighths of the page is data storage, the remaining one eighth being assigned to check bit storage.
摘要翻译： 具有可编程为八（8）或九（9）字节的突发长度的动态随机存取存储器（DRAM）。 DRAM阵列分为两个或更多个子阵列，子阵列单元以可寻址的行和列排列。 当DRAM在正常模式下编程时，突发长度为8，整个阵列地址空间可用于数据存储。 当DRAM被编程用于错误检查（ECC模式）时，突发长度为9，并且阵列被配置为提供第九个字节的阵列的一部分。 在ECC模式下，DRAM的地址空间减少了八分之一。 优选地，所有九个位置在同一页面中，每个页面被分成八个相等的部分。 在正常模式下，所有八个相等的部分都是数据存储; 并且在ECC模式中，页面的七分之一是数据存储，剩下的八分之一被分配给校验位存储。
-
公开(公告)号：US07300825B2
公开(公告)日：2007-11-27
申请号：US10835953
申请日：2004-04-30
IPC分类号： H01L21/00
CPC分类号： H01L21/76895 , H01L24/05 , H01L2224/05624 , H01L2924/12042 , H01L2924/14 , H01L2924/01029 , H01L2924/00
摘要： Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the two wires, then filling the openings with aluminum. The openings can be created (or completed) by a second, maskless UV laser exposure of positive photoresist which is used for patterning the insulating layer. If an opening is not created, an aluminum connecting shape overlying the insulating layer will not effect a connection between the two wires. Similar results can be achieved by laser exposure of a resist used to pattern the aluminum layer, thereby causing breaks in connecting shape when it is desired not to have a connection.
摘要翻译： 在最后一个镶嵌布线层次中的铜线对之间的定制连接是通过在覆盖的绝缘层中形成开口，跨越两条线的部分之间的距离，然后用铝填充开口。 可以通过用于图案化绝缘层的正性光致抗蚀剂的第二次无掩模UV激光曝光来创建（或完成）开口。 如果不产生开口，则覆盖绝缘层的铝连接形状将不会影响两条电线之间的连接。 通过用于图案化铝层的抗蚀剂的激光曝光可以实现类似的结果，从而当期望不连接时，导致连接形状的断裂。
-
公开(公告)号：US06518112B2
公开(公告)日：2003-02-11
申请号：US09899262
申请日：2001-07-06
IPC分类号： H01L31119
CPC分类号： H01L27/11 , H01L21/823885 , H01L21/84 , H01L27/1104 , H01L27/1203 , Y10S257/903
摘要： A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETs; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer. The SRAM cell may be radiation hardened by selectively thickening gate layers to increase storage node capacitance, providing high resistance cell wiring or by including a multi-layered gate oxide layer of NO or ONO, or by any combination thereof.
-
公开(公告)号：US06420925B1
公开(公告)日：2002-07-16
申请号：US09757267
申请日：2001-01-09
IPC分类号： H01H3776
CPC分类号： H03K3/356008 , G11C17/18
摘要： According to the present invention, a programable latch device for use in personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment programmable latch device can use both fuses and antifuses as programmable elements. The programmable latch device provides a solid digital output indicative of the state of the programmable device, and can be reliably read to provide customization and personalization of associated semiconductor devices. The preferred embodiment programable latch device includes an integrated fuse or antifuse as a programmable element in the latch device. By integrating the programmable element into the latch, device size and complexity is minimized. In particular, the number of transistors required drops considerably when compared to prior art approaches.
摘要翻译： 根据本发明，提供了用于个性化半导体器件的可编程锁存器件，其克服了现有技术的限制。 优选实施例可编程锁存器件可以使用熔丝和反熔丝作为可编程元件。 可编程锁存器件提供指示可编程器件状态的实心数字输出，并且可被可靠地读取以提供相关半导体器件的定制和个性化。 优选实施例可编程锁存装置包括作为锁存装置中的可编程元件的集成熔丝或反熔丝。 通过将可编程元件集成到锁存器中，器件尺寸和复杂度最小化。 特别地，与现有技术方法相比，所需的晶体管的数量显着下降。
-
公开(公告)号：US06233184B1
公开(公告)日：2001-05-15
申请号：US09191954
申请日：1998-11-13
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。
-
公开(公告)号：US06177807B1
公开(公告)日：2001-01-23
申请号：US09322465
申请日：1999-05-28
IPC分类号： G03K1716
CPC分类号： G06F13/4086 , H03K5/06 , H04L25/0298
摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.
摘要翻译： 具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。 数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。 具有递增可变长度的传输线短截线连接到控制线14的存储器控制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路 在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。
-
公开(公告)号：US6070262A
公开(公告)日：2000-05-30
申请号：US833367
申请日：1997-04-04
CPC分类号： G11C7/1057 , G06F11/1044 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.
摘要翻译： 动态随机存取存储器（DRAM）可由八（x8）或九（x9）配置。 DRAM具有9个数据输入/输出（I / O）。 存储器阵列被分成两个或更多个子阵列，子阵列单元被布置成可寻址的行和列。 当DRAM被配置为x8时，一个I / O保持在其高阻抗状态; DRAM的数据路径（阵列和第九个I / O之间）的九分之一被忽略; 并且整个阵列地址空间可用于通过八个I / O进行数据存储。 当DRAM配置为x9时，所有9个I / O都有效; DRAM I / O路径被配置为通过第九个I / O提供第九位的阵列的一部分; 并且阵列地址空间减少了八分之一。 所有9位可能来自公共子阵列。 或者，子阵列可以配对，使得当DRAM被配置为x9时，在一个子阵列的七分之八中访问八个比特，其中第九比特在该对的另一个子阵列的八分之一中被访问。
-
公开(公告)号：US6065093A
公开(公告)日：2000-05-16
申请号：US79572
申请日：1998-05-15
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G06F13/00
CPC分类号： G11C7/1072 , G11C7/22
摘要： A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.
摘要翻译： 提供一种存储器件，其堆叠命令并在适当的时间内部执行每个命令，从而确保连续的数据I / O。 存储器件能够立即启动存储器访问或者“堆叠”命令以及“时钟计数”。 时钟计数定义在存储器件执行命令之前必须发生的时钟周期数。 存储器设备立即启动存储器访问，或延迟由该命令的时钟计数定义的时钟数。 存储器件作为存储器控制器的从设备操作，因此在与由存储器控制器定义的时间以外的时间不具有执行指令的能力。
-
公开(公告)号：US5502667A
公开(公告)日：1996-03-26
申请号：US120876
申请日：1993-09-13
申请人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard K. Kalter , Gordon A. Kelley, Jr.
发明人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard K. Kalter , Gordon A. Kelley, Jr.
IPC分类号： H01L25/18 , G11C5/00 , H01L25/00 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11 , G11C5/02
CPC分类号： G11C5/06 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C5/04 , H01L24/49 , H01L25/0657 , H01L2224/05553 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4911 , H01L2224/85207 , H01L2225/0651 , H01L2225/06517 , H01L2225/06551 , H01L2225/06572 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/19041 , H01L2924/19107
摘要： An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译： 一种集成多芯片存储器模块结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得以更高级别的存储器芯片的外观定义更强大的存储器架构。 形成具有N个存储器芯片的存储器子单元，该子单元的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得在模块的I / O引脚上出现具有NxM存储器件的单个存储器芯片架构。 在存储器子单元的一端采用预先形成的电接口层，以将控制逻辑芯片与包括该子单元的存储器芯片电互连。 控制逻辑芯片的尺寸小于包含子单元的存储器芯片的尺寸。 具有延伸穿过其中的内部开口的引线框固定到电接口层，并且控制逻辑芯片固定到电接口层以便驻留在引线框架内，从而产生致密的多芯片集成电路封装。 相应的制造技术包括促进存储器子单元的侧表面上的金属化图案化的方法。
-
-
-
-
-
-
-
-
-
搜索结果
40 条记录 (耗时 0.036 秒)
