公开(公告)号：US06635543B2

公开(公告)日：2003-10-21

申请号：US10335652

申请日：2002-12-31

申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

IPC分类号： A01L21331

CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

摘要翻译： 一种用于在形成于绝缘体上硅（SOI）结构中的沟槽中选择性地生长外延硅的方法和结构。 SOI结构包括在体硅衬底上的掩埋氧化物层（BOX）和BOX上的硅层。 衬垫层形成在硅层上。 焊盘层包括衬垫氧化物（例如，二氧化硅）上的衬垫氮化物（例如，氮化硅），并且衬垫氧化物已经形成在硅层上。 通过各向异性地蚀刻通过焊盘层，硅层，BOX以及体硅衬底内的深度形成沟槽。 绝缘垫片形成在沟槽的侧壁上。 在沟槽中从沟槽的底部到焊盘层的上方生长外延硅层。 去除衬垫层和外延层的部分（例如，通过化学机械抛光），导致外延层的平坦化顶表面与硅层的顶表面大致共面。 电子器件可以形成在沟槽的外延硅内。 这样的电子设备可以包括对浮体效应敏感的动态随机存取存储器（DRAM），双极晶体管，互补金属氧化物半导体（CMOS）电路以及需要阈值电压匹配的器件。 半导体器件（例如，场效应晶体管）可以耦合到沟槽外部的SOI结构。

公开(公告)号：US06566177B1

公开(公告)日：2003-05-20

申请号：US09427257

申请日：1999-10-25

申请人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

发明人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

IPC分类号： H01L2100

CPC分类号： H01L27/10864 ,  H01L27/1087

摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.

摘要翻译： 一种绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元及阵列及其制造方法。 存储单元包括通过自对准埋入带连接到垂直存取晶体管的沟槽存储电容器。 掩埋氧化层将SOI层与硅衬底隔离。 沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。 连接到存储电容器的多晶硅板的多晶硅带提供与存取晶体管的源极的自对准接触。 最初，在晶圆中形成掩埋氧化物层。 深沟槽被蚀刻，最初刚刚通过SOI层和BOX层。 在沟槽中形成保护侧壁。 然后，将深沟槽蚀刻到衬底中。 衬底中的体积被扩大以形成瓶形沟槽。 在深沟槽中形成多晶硅电容器板，并且在电容器板和SOI侧壁之间的沟槽中形成导电多晶硅带。 在晶片中限定器件区域，并且在深沟槽中形成侧壁栅极。 浅沟槽隔离（STI）用于隔离和定义细胞。 在晶片上形成位线和字线。

公开(公告)号：US06426252B1

公开(公告)日：2002-07-30

申请号：US09427256

申请日：1999-10-25

申请人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

发明人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells. Wordlines and bitlines are formed to complete the memory array.

摘要翻译： 绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元，阵列和制造方法。 存储单元包括在分层晶片中的沟槽存储电容器上方的垂直存取晶体管。 形成在硅晶片中的掩埋氧化物（BOX）层将SOI层与硅衬底隔离。 深沟槽通过上表面SOI层，BOX层蚀刻并进入衬底。 每个沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。 在SOI层的BOX层中形成凹部。 凹陷在BOX层中的多晶硅带将每个多晶硅存储电容器板连接到存取晶体管的源极处的自对准接触。 将掺杂剂注入到晶片中以限定器件区域。 存取晶体管栅极沿SOI层侧壁形成。 形成浅沟槽并填充绝缘材料以将细胞与相邻细胞分离。 形成字词和位线以完成内存数组。

公开(公告)号：US5221853A

公开(公告)日：1993-06-22

申请号：US763194

申请日：1991-09-20

申请人： Rajiv V. Joshi ,  Choon-Sik Oh ,  Dan Moy

发明人： Rajiv V. Joshi ,  Choon-Sik Oh ,  Dan Moy

IPC分类号： H01L21/285 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28562 ,  H01L21/76841 ,  H01L2924/0002

摘要： Selective deposition of a refractory metal on a silicon substrate utilizing high temperatures and a silane reduction process in which the flow rate ratio of silane to refractory metal halide gas is less than one. In a second embodiment, an additional layer of the refractory metal is deposited utilizing a hydrogen reduction of the metal halide gas at very high temperatures. In both embodiments, a refractory metal barrier layer may be provided by forming a self-aligned refractory metal silicide layer. Alternatively, a two layer self-aligned barrier is formed of a refractory metal silicide lower layer and a refractory metal nitride upper layer and the refractory metal is selectively deposited on the metal nitride.

摘要翻译： 利用高温选择性地在硅衬底上沉积难熔金属，硅烷还原过程中硅烷与难熔金属卤化物气体的流速比小于1。 在第二实施例中，使用在非常高的温度下的金属卤化物气体的氢还原来沉积难熔金属的附加层。 在两个实施例中，可以通过形成自对准难熔金属硅化物层来提供难熔金属阻挡层。 或者，双层自对准屏障由难熔金属硅化物下层和难熔金属氮化物上层形成，难熔金属选择性地沉积在金属氮化物上。

公开(公告)号：US08569755B2

公开(公告)日：2013-10-29

申请号：US13612938

申请日：2012-09-13

申请人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

发明人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

IPC分类号： H01L29/04

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

摘要翻译： 反熔丝具有一个导电类型的第一和第二半导体区域和它们之间具有相反导电类型的第三半导体区域。 接触第一区域的导电区域在横向于栅极的长尺寸方向的第二方向上具有长尺寸。 反熔丝阳极在第二方向上与第一区域间隔开，并且触点与第二区域连接。 在阳极和接触之间施加编程电压，栅极偏压足以完全导通反熔丝的场效应晶体管操作加热第一区域以向外驱动掺杂剂，导致第一区域的边缘更接近于 并且将第一和第二区域之间的电阻降低一个或多个数量级。

公开(公告)号：US20120171857A1

公开(公告)日：2012-07-05

申请号：US13420724

申请日：2012-03-15

申请人： Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

发明人： Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

IPC分类号： H01L21/768

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

摘要翻译： 制造电可编程熔丝法的制造方法包括在衬底上沉积多晶硅层，图案化阳极接触区域，阴极接触区域和将阴极接触区域与阳极接触区域导电连接的熔断体，其可通过应用 编程电流，在多晶硅层上沉积硅化物层，以及在预定构型中分别在阴极接触区域和阳极接触区域的硅化物层上形成多个不规则接触。

公开(公告)号：US20120012977A1

公开(公告)日：2012-01-19

申请号：US12835764

申请日：2010-07-14

申请人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

发明人： Yan Zun Li ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region. In this way, the antifuse can be configured such that the application of a programming voltage between the anode and the cathode heats the first semiconductor region sufficiently to reach a temperature which drives a dopant outwardly therefrom, causing an edge of the first semiconductor region to move closer to an adjacent edge of the second semiconductor region, thus permanently reducing electrical resistance between the first and second semiconductor regions by one or more orders of magnitude.

摘要翻译： 提供一种具有单一单晶半导体本体的反熔丝，该单体半导体本体包括具有相同的第一导电类型的第一和第二半导体区域以及具有与第一导电类型相反的第二导电类型的第一和第二半导体区域之间的第三半导体区域。 阳极和阴极可以与第一半导体区域电连接。 包括金属，金属的导电化合物或金属的合金的导电区域可以接触第一半导体区域并在阴极和阳极之间延伸。 反熔丝还可以包括与第二半导体区域电连接的触点。 以这种方式，反熔丝可被配置为使得在阳极和阴极之间施加编程电压将第一半导体区域充分加热以达到从其向外驱动掺杂剂的温度，从而使第一半导体区域的边缘移动 更靠近第二半导体区域的相邻边缘，从而将第一和第二半导体区域之间的电阻永久地减小一个或多个数量级。

公开(公告)号：US08004060B2

公开(公告)日：2011-08-23

申请号：US11946938

申请日：2007-11-29

申请人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

发明人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

摘要翻译： 金属层和半导体层顺序地沉积在基板上。 半导体层和金属层被光刻图案化以形成半导体部分和金属栅极部分的堆叠，其优选地与至少一个金属栅极叠层的形成同时进行。 在一个实施例中，半导体部分的尺寸减小，并且金属半导体合金部分通过金属化形成在半导体部分上。 在由此形成的第一电反熔丝中，金属半导体合金部分可以电铸以在金属半导体合金部分和金属栅极部分之间形成短路。 在另一个实施例中，在半导体部分上形成两个非接合的金属半导体合金部分。 在由此形成的第二电反熔丝中，金属半导体合金部分可以被电铸以在两个先前接合的金属半导体合金部分之间形成短路。

公开(公告)号：US07757200B2

公开(公告)日：2010-07-13

申请号：US11941308

申请日：2007-11-16

申请人： Dan Moy ,  Stephen Wu ,  Peter Wang ,  Brian W. Messenger ,  Edwin Soler ,  Gabriel Chiulli

发明人： Dan Moy ,  Stephen Wu ,  Peter Wang ,  Brian W. Messenger ,  Edwin Soler ,  Gabriel Chiulli

IPC分类号： G06F17/50 ,  H01H85/00 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure for an apparatus for programming an electronically programmable semiconductor fuse. The apparatus applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse link.

摘要翻译： 一种用于编程电子可编程半导体保险丝的装置的设计结构。 该装置将编程电流作为一系列多个脉冲施加到熔丝链路。 将编程电流应用为一系列多个短脉冲提供足够高的编程电流电平，以确保可靠且有效的电迁移，同时避免超过熔丝链的温度限制。

公开(公告)号：US20090283840A1

公开(公告)日：2009-11-19

申请号：US12119526

申请日：2008-05-13

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

摘要翻译： 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。