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    Process for producing polyfluoroalkyl ester of unsaturated carboxylic acid
    21.
    发明授权
    Process for producing polyfluoroalkyl ester of unsaturated carboxylic acid 有权
    制备不饱和羧酸多氟烷基酯的方法

    公开(公告)号：US07135592B2

    公开(公告)日：2006-11-14

    申请号：US11191398

    申请日：2005-07-28

    申请人： Katsuyuki Sato ,  Keisuke Kokin ,  Sunao Ikeda ,  Kimihiko Urata

    发明人： Katsuyuki Sato ,  Keisuke Kokin ,  Sunao Ikeda ,  Kimihiko Urata

    IPC分类号： C07C69/52 ,  C07C67/38

    CPC分类号： C07C67/08 ,  C07C69/60 ,  C07C69/593 ,  C07C69/56 ,  C07C69/54

    摘要： A polyfluoroalkyl ester of unsaturated carboxylic acid is produced in high yield in a more simple reactor and with much more reduction in the waste than the conventional process based on esterification reaction by subjecting a polyfluoroalkanol represented by the following general formula: Rf—R—OH where Rf is a polyfluoroalkyl group having 1–6 carbon atoms and R is an alkylene group having 1–6 carbon atoms, and an unsaturated carboxylic acid to dehydration reaction in a fluorine-containing solvent in the presence of an acid catalyst and a polymerization inhibitor.

    摘要翻译： 不饱和羧酸的多氟烷基酯在更简单的反应器中以高产率生产，与通过使由以下通式表示的多氟烷醇进行酯化反应相比，废弃物的还原性大大降低： 公式描述=“在线公式”end =“lead”？> Rf-R-OH <？in-line-formula description =“In-line Formulas”end =“tail”？>其中Rf是具有 1-6个碳原子，R是具有1-6个碳原子的亚烷基，在酸性催化剂和聚合抑制剂存在下，在含氟溶剂中进行不饱和羧酸脱水反应。

    Semiconductor memory device
    22.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US5497353A

    公开(公告)日：1996-03-05

    申请号：US413411

    申请日：1995-03-30

    申请人： Katsuyuki Sato ,  Miki Matsumoto ,  Sadayuki Ohkuma ,  Masahiro Ogata ,  Masahiro Yoshida

    发明人： Katsuyuki Sato ,  Miki Matsumoto ,  Sadayuki Ohkuma ,  Masahiro Ogata ,  Masahiro Yoshida

    IPC分类号： G11C29/00 ,  G11C7/10 ,  G11C7/18 ,  G11C8/10 ,  G11C11/401 ,  G11C29/04 ,  G11C13/00

    CPC分类号： G11C7/18 ,  G11C7/1075 ,  G11C8/10

    摘要： A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.

    Semiconductor memory device including arrangements to facilitate battery backup
    23.
    发明授权
    Semiconductor memory device including arrangements to facilitate battery backup 失效
    半导体存储器件包括便于电池备份的布置

    公开(公告)号：US5323354A

    公开(公告)日：1994-06-21

    申请号：US836597

    申请日：1992-02-18

    申请人： Miki Matsumoto ,  Katsuyuki Sato

    发明人： Miki Matsumoto ,  Katsuyuki Sato

    IPC分类号： G06F12/16 ,  G05F3/24 ,  G11C5/14 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  H03K3/01

    CPC分类号： G11C5/141 ,  G05F3/24 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4085

    摘要： A multi-port memory is provided which is capable of being backed up by a battery to provide a resume function for a digital processor. In a preferred embodiment, a resume function can be provided for a VRAM without restricting the bit rate of image data or the function of the frame memory. Preferably, the memory includes a memory array MARY of memory cells of stereoscopic structure. A high voltage VCH for word line selection can be generated by a voltage-doubling word boost circuit which has its boosting ratio switched stepwise in accordance with the potential of an internal supply voltage. Moreover, a substrate potential generator is provided which has a first substrate potential generator having a relatively low current supplying capacity, which is steadily brought into an operative state, and a second substrate potential generator having a relatively high current supplying capacity which is selectively brought into an operative state. During battery backup, the multi-port memory is in a self-refresh memory. Also, the number of memory mats to be simultaneously activated in the self-refresh mode is made larger than that in the ordinary mode, and a refresh timer circuit RTM for setting the refresh period is of a diffusion layer leakage type.

    摘要翻译： 提供了能够由电池备份以提供数字处理器的恢复功能的多端口存储器。 在优选实施例中，可以为VRAM提供恢复功能，而不限制图像数据的比特率或帧存储器的功能。 优选地，存储器包括立体结构的存储器单元的存储器阵列MARY。 用于字线选择的高电压VCH可以通过倍压字升压电路产生，该升压电路的升压比根据内部电源电压的电位逐步切换。 此外，提供了具有稳定地进入操作状态的具有相对低的电流供应能力的第一衬底电位发生器的衬底电位发生器和具有相对高的电流供应能力的第二衬底电位发生器，该第二衬底电位发生器选择性地被引入 操作状态 在备份电池期间，多端口存储器处于自刷新存储器中。 而且，在自刷新模式下同时激活的存储器垫的数量大于普通模式，并且用于设置刷新周期的刷新定时器电路RTM具有扩散层泄漏型。

    Semiconductor memory device
    24.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5289428A

    公开(公告)日：1994-02-22

    申请号：US972913

    申请日：1992-11-06

    申请人： Katsuyuki Sato ,  Miki Matsumoto ,  Sadayuki Ohkuma ,  Masahiro Ogata ,  Masahiro Yoshida

    发明人： Katsuyuki Sato ,  Miki Matsumoto ,  Sadayuki Ohkuma ,  Masahiro Ogata ,  Masahiro Yoshida

    IPC分类号： G11C29/00 ,  G11C7/10 ,  G11C7/18 ,  G11C8/10 ,  G11C11/401 ,  G11C29/04 ,  G11C13/00

    CPC分类号： G11C7/18 ,  G11C7/1075 ,  G11C8/10

    摘要： A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers for the serial input/output lines are provided at upper and lower ends of the serial access memory elements to respectively amplify signals from the divided lines. Additional features are provided for improving both the serial and random operation. For example, during the serial read mode, the column selector for random access is simultaneously operated, and read data passing through the random access column selector is used as head data for the serial output operation to be delivered through the serial output circuit. Also, a serial selector can be controlled by a select signal formed by a Gray Code counter to improve operating speed. Further features included a redundancy system for relief of defective bits, the use of common bit lines to improve integration density and an improved refreshing arrangement to reduce power consumption during the refresh mode.

    摘要翻译： 提供多端口存储器，允许随机访问和串行访问。 为了减少寄生电容并提高工作速度，串行输入/输出线在其中间点分为两部分。 用于串行输入/输出线的读出放大器设置在串行存取存储器元件的上端和下端，以分别放大来自分割线的信号。 提供了另外的功能来改进串行和随机操作。 例如，在串行读取模式期间，用于随机存取的列选择器被同时操作，并且通过随机存取列选择器的读数据被用作通过串行输出电路传送的串行输出操作的头数据。 此外，串行选择器可以由格雷码计数器形成的选择信号控制，以提高操作速度。 其他特征包括用于缓解缺陷位的冗余系统，使用公共位线来提高集成密度以及改进的刷新布置以减少刷新模式期间的功耗。

    Semiconductor memory
    25.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5249159A

    公开(公告)日：1993-09-28

    申请号：US744512

    申请日：1991-08-13

    申请人： Katsuyuki Sato

    发明人： Katsuyuki Sato

    IPC分类号： G11C7/10 ,  G11C11/4096

    CPC分类号： G11C7/1075 ,  G11C11/4096

    摘要： A semiconductor memory, such as, of a dual-port type includes RAM cells in which each RAM cell is coupled to one of a plurality of data lines and a word line. The memory is also associated with a plurality of sense amplifiers which are respectively coupled to a correspondingly associated data line, a plurality of switches respectively coupled between the plurality of data lines and a common data line for providing either a selective or simultaneous connection of the plurality of data lines to the common data line during a first write mode and a second write mode, respectively, a write circuit coupled between an external input/output terminal and the common data line which provides the first write signal having a first two-level signal range in accordance with the first write mode and a second write signal having a second two-level signal range in accordance with a second write mode. The memory also has a control circuit, such as a random access port column address decoder, which is responsive to column address signals for providing data line selecting signals for simultaneously turning ON each one of the plurality of switches during the normal operation of the memory or, alternatively, providing data line selecting signals for selectively turning ON a respective column switch during a normal operation thereof. The semiconductor memory is also additionally provided with a serial output circuit having a parallel-to-parallel circuit converter coupling the plurality of data lines therethrough to a serial input/output port external terminal.

    摘要翻译： 诸如双端口类型的半导体存储器包括其中每个RAM单元耦合到多条数据线和字线之一的RAM单元。 存储器还与分别耦合到对应相关联的数据线的多个读出放大器相关联，分别耦合在多个数据线之间的多个开关和用于提供多个数据线的选择性或同时连接的公共数据线 分别在第一写入模式和第二写入模式期间到公共数据线的数据线，耦合在外部输入/输出端子和公共数据线之间的写入电路，其提供具有第一二级信号的第一写入信号 根据第一写入模式的范围和具有根据第二写入模式的第二二级信号范围的第二写入信号。 存储器还具有诸如随机存取端口列地址解码器的控制电路，其响应于列地址信号，用于提供数据线选择信号，以在存储器的正常操作期间同时接通多个开关中的每一个， 或者，提供数据线选择信号，用于在其正常操作期间选择性地接通相应的列开关。 半导体存储器还附加地设置有串行输出电路，该串行输出电路具有将多个数据线通过其并入到串行输入/输出端口外部端子的并联电路转换器。

    Process for producing semiconductor memory device
    27.
    发明授权
    Process for producing semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US5079181A

    公开(公告)日：1992-01-07

    申请号：US397847

    申请日：1989-08-24

    申请人： Shinji Shimizu ,  Osamu Tsuchiya ,  Katsuyuki Sato

    发明人： Shinji Shimizu ,  Osamu Tsuchiya ,  Katsuyuki Sato

    IPC分类号： G11C7/18 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  G11C7/18 ,  H01L27/10805 ,  H01L29/66181 ,  Y10S257/906

    摘要： Dynamic RAM having memory cells, each of the memory cells having a capacitor with the electrode comprised of a first semiconductor region of a first type of conductivity formed in a substrate of second conductivity type. The first semiconductor region is formed by introducing impurities using a mask comprising (1) a nitride film which is deposited so as to define part of the shape of the capacitor. An oxide film, formed by thermal oxidation of the substrate, defines the shape of the memory cells, and each of the memory cells further have at least a second semiconductor region of a second type of conductivity formed between and under the electrodes, the shape thereof being defined by the nitride film and the oxide film that is formed by thermal oxidation.

    Selective application of voltages for testing storage cells in semiconductor memory arrangements
    30.
    发明授权
    Selective application of voltages for testing storage cells in semiconductor memory arrangements 失效
    选择性地应用电压以测试半导体存储器布置中的存储单元

    公开(公告)号：US4839865A

    公开(公告)日：1989-06-13

    申请号：US934666

    申请日：1986-11-24

    申请人： Katsuyuki Sato ,  Hiroshi Kawamoto ,  Kazumasa Yanagisawa

    发明人： Katsuyuki Sato ,  Hiroshi Kawamoto ,  Kazumasa Yanagisawa

    IPC分类号： G11C11/401 ,  G11C11/404 ,  G11C11/4074 ,  G11C29/00 ,  G11C29/50

    CPC分类号： G11C29/50016 ,  G11C11/4074 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

    摘要： A dynamic RAM is provided with a plurality of 1-MOSFET memory cells, each having a storage capacitor and a switching MOSFET coupled to one electrode of the storage capacitor. The other electrode of each of the storage capacitors is coupled to a switching circuit which controls the voltage which is applied to the capacitor. The switching circuit is, in turn, coupled to both a voltage generating circuit (which preferably provides a voltage of 1/2 Vcc) and a voltage supply circuit which is set to provide predetermined test voltages. Thus, by operating the switching circuit, a voltage of 1/2 Vcc can be applied to the memory cell capacitors during normal operation of the dynamic RAM, and the predetermined test voltages can be applied to the memory cell capacitors during a testing operation.

    摘要翻译： 动态RAM设置有多个1-MOSFET存储单元，每个具有存储电容器和耦合到存储电容器的一个电极的开关MOSFET。 每个存储电容器的另一个电极耦合到控制施加到电容器的电压的开关电路。 开关电路又耦合到电压产生电路（其优选地提供1/2Vcc的电压）和被设置为提供预定测试电压的电压供应电路两者。 因此，通过操作开关电路，在动态RAM的正常操作期间可以向存储单元电容器施加1/2Vcc的电压，并且可以在测试操作期间将预定的测试电压施加到存储单元电容器。