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39 条记录 (耗时 0.028 秒)

    Process for fabricating circuit assemblies using electrodepositable dielectric coating compositions
    22.
    发明授权
    Process for fabricating circuit assemblies using electrodepositable dielectric coating compositions 失效
    使用电沉积介电涂层组合物制造电路组件的方法

    公开(公告)号：US07000313B2

    公开(公告)日：2006-02-21

    申请号：US10184192

    申请日：2002-06-27

    申请人： Gregory J. McCollum ,  Thomas C. Moriarity ,  Kevin C. Olson ,  Michael G. Sandala ,  Alan E. Wang ,  Steven R. Zawacky

    发明人： Gregory J. McCollum ,  Thomas C. Moriarity ,  Kevin C. Olson ,  Michael G. Sandala ,  Alan E. Wang ,  Steven R. Zawacky

    IPC分类号： H01K3/10

    CPC分类号： H05K3/44 ,  H01L2924/0002 ,  H05K1/056 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/445 ,  H05K2201/09554 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

    摘要： Provided is a process for forming metallized vias in a substrate including the steps of (I) applying to an electroconductive substrate an electrodepositable coating composition onto all exposed surfaces of the substrate to form a conformal dielectric coating; (II) ablating a surface of the dielectric coating to expose a section of the substrate; (III) applying a layer of metal to all surfaces to form metallized vias in the substrate. Also disclosed are processes for fabricating a circuit assembly which include the application of an electrodoepositable coating composition onto exposed surfaces of the substrate/core to form a conformal dielectric coating thereon. The electrodepositable coating composition includes a resinous phase dispersed in an aqueous phase, where the resinous phase has a covalently bonded halogen content of at least 1 percent by weight. The dielectric coating derived therefrom has a low dielectric constant and low dielectric loss factor.

    摘要翻译： 提供了一种用于在基底中形成金属化通孔的方法，包括以下步骤：（I）将可电沉积涂料组合物施加到导电基底上，以在基底的所有暴露表面上形成共形绝缘涂层; （II）烧蚀所述电介质涂层的表面以暴露所述衬底的一部分; （III）将金属层施加到所有表面以在基底中形成金属化通孔。 还公开了用于制造电路组件的方法，其包括将电沉积涂料组合物施加到基材/芯的暴露表面上以在其上形成共形绝缘涂层。 电沉积涂料组合物包括分散在水相中的树脂相，其中树脂相具有至少1重量％的共价键合的卤素含量。 由此得到的电介质涂层具有低介电常数和低介电损耗因子。

    Method of forming solid blind vias through the dielectric coating on high density interconnect substrate materials
    25.
    发明授权
    Method of forming solid blind vias through the dielectric coating on high density interconnect substrate materials 失效
    通过高密度互连衬底材料上的介电涂层形成固体盲孔的方法

    公开(公告)号：US08008188B2

    公开(公告)日：2011-08-30

    申请号：US11760804

    申请日：2007-06-11

    申请人： Kevin C. Olson ,  Alan E. Wang

    发明人： Kevin C. Olson ,  Alan E. Wang

    IPC分类号： H01L21/4763

    CPC分类号： H05K3/44 ,  H05K3/108 ,  H05K3/388 ,  H05K3/445 ,  H05K3/4647 ,  H05K2201/09554 ,  H05K2203/0582 ,  H05K2203/0733 ,  H05K2203/135

    摘要： A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portions of the electrically conductive core, coating the conductive material with a second removable material, removing the first removable material, electrophoretically coating the electrically conductive core with a dielectric coating, and removing the second removable material.

    摘要翻译： 提供了一种方法，包括：用第一可移除材料涂覆导电芯，在第一可移除材料中形成开口以暴露部分导电芯，将导电材料镀在导电芯的暴露部分上， 具有第二可移除材料的材料，去除第一可移除材料，用电介质涂层电泳涂覆导电芯，以及去除第二可除去材料。

    Method for creating circuit assemblies
    28.
    发明申请
    Method for creating circuit assemblies 审中-公开
    创建电路组件的方法

    公开(公告)号：US20060141143A1

    公开(公告)日：2006-06-29

    申请号：US11280376

    申请日：2005-11-16

    申请人： Gregory J. McCollum ,  Thomas C. Moriarity ,  Kevin C. Olson ,  Michael G. Sandala

    发明人： Gregory J. McCollum ,  Thomas C. Moriarity ,  Kevin C. Olson ,  Michael G. Sandala

    IPC分类号： B05D5/06

    CPC分类号： H05K1/056 ,  H05K3/4676 ,  H05K2203/135

    摘要： Provided is a method for preparing a circuit assembly. The method includes (a) applying a curable coating composition to a substrate, the curable coating composition formed from (i) one or more active hydrogen-containing resins, (ii) one or more polyester curing agents, and (iii) optionally, one or more transesterification catalysts; (b) curing the curable coating composition to form a coating on the substrate; and (c) applying a conductive layer to the surface of at least part of said cured composition. A circuit assembly prepared by the method also is provided.

    摘要翻译： 提供了一种制备电路组件的方法。 该方法包括（a）将可固化涂料组合物施用到基材上，所述可固化涂料组合物由（i）一种或多种含活性氢的树脂，（ii）一种或多种聚酯固化剂，和（iii）任选的一种 或更多的酯交换催化剂; （b）固化可固化涂料组合物以在基材上形成涂层; 和（c）将导电层施加到所述固化的组合物的至少一部分的表面上。 还提供了一种通过该方法制备的电路组件。

    Process for creating holes in polymeric substrates
    29.
    发明授权
    Process for creating holes in polymeric substrates 失效
    在聚合物基材中形成孔的方法

    公开(公告)号：US06824959B2

    公开(公告)日：2004-11-30

    申请号：US10183674

    申请日：2002-06-27

    申请人： Kevin C. Olson ,  Alan E. Wang

    发明人： Kevin C. Olson ,  Alan E. Wang

    IPC分类号： G03F700

    CPC分类号： H05K3/002 ,  H05K3/4644 ,  Y10T428/12361 ,  Y10T428/24322

    摘要： Provided is a process for creating a via through a substrate including the steps of (a) providing a substantially void-free film of a curable composition; (b) applying a resist onto the curable film; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the curable film; (e) removing the exposed areas of the curable film to form holes through the curable film; and (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition. Also disclosed is a process of fabricating a circuit assembly which includes building patterned circuit layers upon a substrate that has vias provided by the aformentioned process.

    摘要翻译： 提供了一种通过基板形成通孔的方法，包括以下步骤：（a）提供可固化组合物的基本上无空隙的膜; （b）将抗蚀剂涂布在可固化膜上; （c）在预定位置对抗蚀剂进行成像; （d）显影抗蚀剂以暴露可固化膜的预定区域; （e）去除可固化膜的暴露区域以形成穿过可固化膜的孔; 和（f）将步骤（e）的可固化膜加热至足以固化可固化组合物的温度和时间。 还公开了一种制造电路组件的方法，其包括在具有由上述工艺提供的通孔的基板上构建图案化电路层。

    Multi-layer circuit assembly and process for preparing the same
    30.
    发明授权
    Multi-layer circuit assembly and process for preparing the same 失效
    多层电路组装及其制备方法

    公开(公告)号：US06671950B2

    公开(公告)日：2004-01-06

    申请号：US09901373

    申请日：2001-07-09

    申请人： Lance C. Sturni ,  Kevin C. Olson

    发明人： Lance C. Sturni ,  Kevin C. Olson

    IPC分类号： H01K310

    CPC分类号： C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/142 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  H01L2924/00

    摘要： A process for fabricating a multi-layer circuit assembly is provided comprising the following steps: (a) providing a perforate electrically conductive core having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the electrically conductive core to form a conformal coating on all exposed surfaces of the electrically conductive core; (c) ablating the surface of the dielectric coating in a predetermined pattern to expose sections of the electrically conductive core; (d) applying a layer of metal to all surfaces to form metallized vias through the electrically conductive core; and (e) applying a resinous photosensitive layer to the metal layer. Additional processing steps such as circuitization may be included. Also provided are multi-layer circuit assemblies produced by the process of the present invention, comprising component layers having high via density and thermal coefficients of expansion that are compatible with those of semiconductor chips and rigid wiring boards which may be attached as components of the circuit assembly.

    摘要翻译： 提供一种制造多层电路组件的方法，包括以下步骤：（a）提供具有500至10,000个孔/平方英寸（75至1550个孔/平方厘米）的通孔密度的穿孔导电芯;（b ）在所述导电芯的所有暴露表面上施加电介质涂层以在所述导电芯的所有暴露表面上形成共形涂层;（c）以预定图案烧蚀所述电介质涂层的表面以暴露所述导电芯部分 芯;（d）将金属层施加到所有表面以通过导电芯形成金属化通孔; 另外还可以包括诸如电路化的其它处理步骤。还提供了通过本发明的方法生产的多层电路组件，其包括具有高通孔密度和热量的组分层 与可以作为电路组件的组件附接的半导体芯片和刚性线路板的扩展系数相容。