公开(公告)号：US07622403B2

公开(公告)日：2009-11-24

申请号：US11613155

申请日：2006-12-19

申请人： Yasri Yudhistira ,  Johnny Widodo ,  Bei Chao Zhang ,  Liang-Choo Hsia

发明人： Yasri Yudhistira ,  Johnny Widodo ,  Bei Chao Zhang ,  Liang-Choo Hsia

IPC分类号： H01L21/00

CPC分类号： G03F7/0035 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76825 ,  H01L2221/1047

摘要： A semiconductor processing system with ultra low-K dielectric is provided including providing a substrate having an electronic circuit, forming an ultra low-K dielectric layer, having porogens, over the substrate, blocking an incoming radiation from a first region of the ultra low-K dielectric layer, evaporating the porogens from a second region of the ultra low-K dielectric layer by projecting the incoming radiation on the second region, and removing the ultra low-K dielectric layer in the first region with a developer.

摘要翻译： 提供了一种具有超低K电介质的半导体处理系统，包括提供具有电子电路的衬底，在衬底上形成具有致孔剂的超低K电介质层，阻挡来自超低K电介质的第一区域的入射辐射， K电介质层，通过将入射辐射投射在第二区域上，从超低K电介质层的第二区域蒸发致孔剂，并用显影剂除去第一区域中的超低K电介质层。

公开(公告)号：US20090239369A1

公开(公告)日：2009-09-24

申请号：US12051223

申请日：2008-03-19

申请人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

发明人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

IPC分类号： H01L21/31 ,  H01L21/44

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76814 ,  H01L2221/1063

摘要： Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.

摘要翻译： 形成具有电互连的集成电路器件的方法包括在衬底上形成电绝缘层并在电绝缘层上形成硬掩模。 使用掩模依次选择性地蚀刻硬掩模和电绝缘层，以在其中限定开口。 该开口（其可以是通孔）暴露硬掩模和电绝缘层的内侧壁。 然后硬掩模的内侧壁相对于电绝缘层的内侧壁凹陷，并且牺牲反应层形成在电绝缘层的内侧壁上。 该反应层操作以使电绝缘层的内侧壁凹陷。 然后去除反应层以限定具有相对均匀侧壁的较宽开口。 然后用更宽的开口填充电互连。

公开(公告)号：US20080230907A1

公开(公告)日：2008-09-25

申请号：US11690080

申请日：2007-03-22

申请人： Wuping Liu ,  Kevin S. Petrarca ,  Johnny Widodo ,  Lawrence A. Clevenger ,  Wai-Kin Li

发明人： Wuping Liu ,  Kevin S. Petrarca ,  Johnny Widodo ,  Lawrence A. Clevenger ,  Wai-Kin Li

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a carbon implant region around the via opening, a trench opening, or a combination thereof, for protecting the low-K dielectric layer.

摘要翻译： 提供一种集成电路硬掩模处理系统，包括提供具有集成电路的基板; 在所述集成电路上形成互连层; 在所述互连层上施加低K电介质层; 形成通过所述低K电介质层的通孔到所述互连层; 以及在通孔开口周围形成碳注入区域，沟槽开口或其组合，用于保护低K电介质层。

公开(公告)号：US20080220584A1

公开(公告)日：2008-09-11

申请号：US11683590

申请日：2007-03-08

申请人： Jun-jung Kim ,  Ja-hum Ku ,  Jae-eon Park ,  Sunfei Fang ,  Alois Gutmann ,  O-sung Kwon ,  Johnny Widodo ,  Dae-won Yang

发明人： Jun-jung Kim ,  Ja-hum Ku ,  Jae-eon Park ,  Sunfei Fang ,  Alois Gutmann ,  O-sung Kwon ,  Johnny Widodo ,  Dae-won Yang

IPC分类号： H01L29/82

CPC分类号： H01L21/0217 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823425

摘要： Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.

摘要翻译： 形成集成电路器件的方法包括在其上具有集成电路结构的集成电路衬底上沉积电绝缘层。 该沉积步骤导致形成具有起伏表面轮廓的电绝缘层，该电绝缘层包括至少一个峰和至少与至少一个峰相邻的峰。 然后进行非均匀的增稠步骤。 这种不均匀的增厚步骤包括通过将电绝缘层的部分从至少一个峰重新沉积到至少一个谷部来增厚电绝缘层的一部分。 使用利用电绝缘层作为溅射靶的溅射沉积技术发生这种再沉积。

公开(公告)号：US20110156110A1

公开(公告)日：2011-06-30

申请号：US13043059

申请日：2011-03-08

申请人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

发明人： Jun-jung Kim ,  Sang-jine Park ,  Min-ho Lee ,  Thomas W. Dyer ,  Sunfei Fang ,  O-sung Kwon ,  Johnny Widodo

IPC分类号： H01L29/772

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7843

摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.

摘要翻译： 形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。 当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。 然后从栅电极的侧壁去除牺牲隔离物。 然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管） 。

公开(公告)号：US07847402B2

公开(公告)日：2010-12-07

申请号：US11676522

申请日：2007-02-20

申请人： Darryl D. Restaino ,  Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Jae H. Kim ,  Michael W. Lane ,  Xiao H. Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Johnny Widodo

发明人： Darryl D. Restaino ,  Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Jae H. Kim ,  Michael W. Lane ,  Xiao H. Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Johnny Widodo

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/53295 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

摘要翻译： 提供了包括后端行（“BEOL”）互连结构的芯片。 BEOL互连结构包括多个层间电介质（“ILD”）层，其包括通过紫外线（“UV”）辐射固化的电介质材料。 多个金属互连配线层嵌入在多个ILD层中。 介电阻挡层覆盖多个金属互连布线层，介电阻挡层适于减少材料在金属互连布线层和ILD层之间的扩散。 介质阻挡层中的一个适于保持压缩应力，同时承受足以固化ILD层的介电材料的UV辐射，使得BEOL结构更好地能够避免由于热和/或机械应力引起的变形。

公开(公告)号：US07737029B2

公开(公告)日：2010-06-15

申请号：US12050354

申请日：2008-03-18

申请人： Jae-hak Kim ,  Griselda Bonilla ,  Steven E. Molis ,  Darryl D. Restaino ,  Hosadurga Shobha ,  Johnny Widodo

发明人： Jae-hak Kim ,  Griselda Bonilla ,  Steven E. Molis ,  Darryl D. Restaino ,  Hosadurga Shobha ,  Johnny Widodo

IPC分类号： H01L21/321

CPC分类号： H01L23/53233 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76876 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 Å to about 50 Å and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.

摘要翻译： 形成器件的方法包括在衬底上形成其中具有金属互连的第一电绝缘层，然后在金属互连的上表面上和第一电绝缘层上形成第一电绝缘阻挡层。 第一电绝缘阻挡层暴露于穿过第一电绝缘屏障并从金属互连的上表面除去氧的等离子体。 阻挡层的厚度可以在约5至约埃的范围内，等离子体可以是将金属互连的上表面上的氧转化为水的含氢等离子体。

公开(公告)号：US20090315115A1

公开(公告)日：2009-12-24

申请号：US12214854

申请日：2008-06-23

申请人： Beichao Zhang ,  Johnny Widodo ,  Juan Boon Tan ,  Yong Kong Siew ,  Fan Zhang ,  Haifeng Sheng ,  Wenhe Lin ,  Young Way Teh ,  Jinping Liu ,  Vincent Ho ,  Liang Choo Hsia

发明人： Beichao Zhang ,  Johnny Widodo ,  Juan Boon Tan ,  Yong Kong Siew ,  Fan Zhang ,  Haifeng Sheng ,  Wenhe Lin ,  Young Way Teh ,  Jinping Liu ,  Vincent Ho ,  Liang Choo Hsia

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L29/7846

摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.

摘要翻译： 制造半导体器件的方法（和半导体器件）通过在STI区域中注入离子来提供浅沟槽隔离（STI）结构或区域。 在植入之后，区域（衬底材料和不同元素的离子）进行热退火，产生用于隔离两个相邻的场效应晶体管（FET）的电介质材料。 这消除了去除衬底材料以形成沟槽并用电介质材料重新填充沟槽的常规步骤。 将氮离子注入到邻近p型FET的STI区域中，对晶体管沟道区域施加压缩应力以增强晶体管性能。 将氧离子注入到与n型FET相邻的STI区域中，对晶体管沟道区域施加拉伸应力以增强晶体管性能。

公开(公告)号：US07524755B2

公开(公告)日：2009-04-28

申请号：US11358934

申请日：2006-02-22

申请人： Johnny Widodo ,  Bei Chao Zhang ,  Tong Qing Chen ,  Yong Kong Siew ,  Fan Zhang ,  San Leong Liew ,  John Sudijono ,  Liang Choo Hsia

发明人： Johnny Widodo ,  Bei Chao Zhang ,  Tong Qing Chen ,  Yong Kong Siew ,  Fan Zhang ,  San Leong Liew ,  John Sudijono ,  Liang Choo Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05073 ,  H01L2224/05546 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/01039 ,  H01L2924/00

摘要： A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.

摘要翻译： 形成用于互连的CuSiN构成的阻挡层和盖的方法。 我们在半导体结构上的电介质层中提供互连开口。 通过与第一铜层反应，在互连开口的侧壁和底部上形成CuSiN阻挡层。 然后，我们在填充互连开口的CuSiN层上形成互连。 我们可以在互连的顶部表面上形成CuSiN覆盖层。

公开(公告)号：US20080197513A1

公开(公告)日：2008-08-21

申请号：US11676522

申请日：2007-02-20

申请人： Darryl D. Restaino ,  Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Jae H. Kim ,  Michael W. Lane ,  Xiao H. Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Johnny Widodo

发明人： Darryl D. Restaino ,  Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Jae H. Kim ,  Michael W. Lane ,  Xiao H. Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Johnny Widodo

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L23/53295 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

摘要翻译： 提供了包括后端行（“BEOL”）互连结构的芯片。 BEOL互连结构包括多个层间电介质（“ILD”）层，其包括通过紫外线（“UV”）辐射固化的电介质材料。 多个金属互连配线层嵌入在多个ILD层中。 介电阻挡层覆盖多个金属互连布线层，介电阻挡层适于减少材料在金属互连布线层和ILD层之间的扩散。 介质阻挡层中的一个适于保持压缩应力，同时承受足以固化ILD层的介电材料的UV辐射，使得BEOL结构更好地能够避免由于热和/或机械应力引起的变形。