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公开(公告)号：US12218665B2
公开(公告)日：2025-02-04
申请号：US18181983
申请日：2023-03-10
Applicant: Macronix International Co., Ltd.
Inventor： Yi-Fan Chang , Su-Chueh Lo , Jeng-Kuan Lin
Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.
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公开(公告)号：US12166486B2
公开(公告)日：2024-12-10
申请号：US17983738
申请日：2022-11-09
Applicant: Macronix International Co., Ltd.
Inventor： Wei-Yi Cheng , Su-Chueh Lo
Abstract: Systems, methods, circuits, and apparatus for managing signal transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: one or more target units each configured to receive a signal and a plurality of inverting units arranged on signal paths to the one or more target units. For each of the one or more target units, one or more corresponding inverting units of the plurality of inverting units are configured to invert the signal multiple times along a corresponding signal path to the target unit to cause a signal width of the inverted signal received by the target unit to be substantially identical to a signal width of the signal.
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公开(公告)号：US20210349645A1
公开(公告)日：2021-11-11
申请号：US16870848
申请日：2020-05-08
Applicant: MACRONIX International Co., Ltd.
Inventor： Chun-Hsiung Hung , Su-Chueh Lo
IPC: G06F3/06 , H01L25/065
Abstract: A multi-die memory apparatus and identification method thereof are provided. The identification method includes: sending an identification initial command and a first start command to a plurality of memory devices by a controller for starting a first identification period; respectively generating a plurality of first target numbers by the memory devices; respectively performing first counting actions and comparing a plurality of first counting numbers with the first target numbers by a plurality of un-identified memory devices to set a first time-up memory device of the memory devices; and, setting an identification code of the first time-up memory device of the un-identified memory devices to be a first value.
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公开(公告)号：US10658046B2
公开(公告)日：2020-05-19
申请号：US15841622
申请日：2017-12-14
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuen-Long Chang , Ken-Hui Chen , Su-Chueh Lo , Chun-Yu Liao
Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.
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公开(公告)号：US10185697B2
公开(公告)日：2019-01-22
申请号：US15006316
申请日：2016-01-26
Applicant: Macronix International Co., Ltd.
Inventor： Shang-Chi Yang , Su-Chueh Lo
Abstract: A memory device comprises an output buffer and a control circuit. The control circuit is configured to receive a system clock signal at an input of the control circuit. The control circuit is configured to generate a data transition signal based on the system clock signal. The control circuit is configured to provide the data transition signal to the output buffer of the memory device. The output buffer is configured to output memory data based on the data transition signal.
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Patent Agency Ranking
公开(公告)号：US20150220390A1
公开(公告)日：2015-08-06
申请号：US14173873
申请日：2014-02-06
Applicant: Macronix International Co., Ltd.
Inventor： Chien-Hsin Liu , Su-Chueh Lo , Kuen-Long Chang , Ken-Hui Chen , Chun-Hsiung Hung
CPC classification number: G06F11/1072 , G06F11/1012 , H03M13/1575 , H03M13/19
Abstract: A programming method, a reading method and an operating system for a memory are provided. The programming method includes the following steps. A data is provided. A parity generation is performed to obtain an error-correcting code (ECC). The memory is programmed to record the data and the error-correcting code. The data is transformed before performing the parity generation, such that a hamming distance between two codes corresponding to two adjacent threshold voltage states in the data to be performed the parity generation is 1.
Abstract translation: 提供了一种用于存储器的编程方法，读取方法和操作系统。 编程方法包括以下步骤。 提供数据。 执行奇偶校验生成以获得纠错码（ECC）。 存储器被编程为记录数据和纠错码。 在执行奇偶校验生成之前变换数据，使得对应于待执行奇偶产生的数据中的两个相邻阈值电压状态的两个代码之间的汉明距离为1。
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公开(公告)号：US20250119142A1
公开(公告)日：2025-04-10
申请号：US18988186
申请日：2024-12-19
Applicant: Macronix International Co., Ltd.
Inventor： Yi-Fan Chang , Su-Chueh Lo , Jeng-Kuan Lin
IPC: H03K19/0185 , G06F3/06 , G11C7/10 , H03K3/037 , H03K19/00
Abstract: Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, a method includes: selecting a first interface to receive higher-speed-type data at a first clock frequency; transferring the higher-speed-type data with a first speed along a first data path from the first interface through a first logic circuit to a driving circuit; outputting the higher-speed-type data by the driving circuit; selecting a second interface to receive lower-speed-type data at a second clock frequency that is same as the first clock frequency; transferring the lower-speed-type data with a second speed along a second data path from the second interface through a second logic circuit to the driving circuit, the first speed being higher than the second speed; and outputting the lower-speed-type data by the driving circuit.
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公开(公告)号：US20250105832A1
公开(公告)日：2025-03-27
申请号：US18475244
申请日：2023-09-27
Applicant: MACRONIX International Co., Ltd.
Inventor： Su-Chueh Lo , Jhen-Sheng Chih
Abstract: A duty cycle correction method and a duty cycle correction system, adapted for correcting a duty cycle of a clock signal by using a duty cycle corrector (DCC) in a high-capacity and high-performance semiconductor product such as a 3D NAND flash, are provided. In the method, training is performed on the DCC to correct the clock signal, and a training result is recorded after the training is finished; and the DCC is updated by the recorded training result before a next toggle of the clock signal.
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公开(公告)号：US11984371B2
公开(公告)日：2024-05-14
申请号：US18341957
申请日：2023-06-27
Applicant: Macronix International Co., Ltd.
Inventor： Chun-Hsiung Hung , Su-Chueh Lo
IPC: H01L21/66 , G01R31/28 , H01L23/00 , H01L23/498
CPC classification number: H01L22/32 , G01R31/2896 , H01L23/49811 , H01L23/49838 , H01L24/16 , H01L2224/1623
Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. In one aspect, a chiplet system includes multiple integrated circuit devices electrically connected together. The integrated circuit devices include an integrated circuit device including: an integrated circuit, a plurality of first type bonding pads electrically connected to the integrated circuit and electrically connected to at least one other of the integrated circuit devices, and one or more second type bonding pads electrically isolated from the at least one other of the integrated circuit devices. At least one of the plurality of first type bonding pads is configured to be electrically connected to a corresponding one of the one or more second type bonding pads.
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公开(公告)号：US20240154607A1
公开(公告)日：2024-05-09
申请号：US17983738
申请日：2022-11-09
Applicant: Macronix International Co., Ltd.
Inventor： Wei-Yi Cheng , Su-Chueh Lo
CPC classification number: H03K3/037 , G06F13/1684 , G11C16/10 , G11C16/32 , H03K5/13 , H03K19/21 , G11C16/0483
Abstract: Systems, methods, circuits, and apparatus for managing signal transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: one or more target units each configured to receive a signal and a plurality of inverting units arranged on signal paths to the one or more target units. For each of the one or more target units, one or more corresponding inverting units of the plurality of inverting units are configured to invert the signal multiple times along a corresponding signal path to the target unit to cause a signal width of the inverted signal received by the target unit to be substantially identical to a signal width of the signal.
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