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公开(公告)号：US20160239262A1
公开(公告)日：2016-08-18
申请号：US15041038
申请日：2016-02-11
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Hillel Chapman
Abstract: Apparatus, systems, and methods are described, including apparatus that includes one or more communication interfaces for communicating over a communication network, and a processor. The processor is configured to receive, via the communication interfaces, a plurality of numbers, and calculate a sum of the numbers that is independent of an order in which the numbers are received, by (i) converting any of the numbers that are received in a floating-point representation to a derived floating-point representation that includes a plurality of signed integer multiplicands corresponding to different respective orders of magnitude, and (ii) summing the numbers in the derived floating-point representation, by separately summing integer multiplicands that correspond to the same order of magnitude. Other embodiments are also described.
Abstract translation: 描述了装置，系统和方法，包括包括用于通过通信网络进行通信的一个或多个通信接口和处理器的装置。 处理器被配置为经由通信接口接收多个数字，并且通过以下步骤来计算与接收数字无关的顺序的数字的和：（i）将在 对衍生浮点表示的浮点表示，其包括对应于不同相应数量级的多个带符号整数被乘数，以及（ii）通过对应于对应的整数被乘数来对导出的浮点表示中的数进行求和 达到相同的数量级。 还描述了其它实施例。
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公开(公告)号：US20250047402A1
公开(公告)日：2025-02-06
申请号：US18229074
申请日：2023-08-01
Applicant: Mellanox Technologies, Ltd.
Inventor： Yam Gellis , Oren Matus , Liron Mula , Natan Manevich , Hillel Chapman , Dotan David Levi
IPC: H04J3/06
Abstract: A device includes a receiver including a timestamp generator to update timestamps at a first rate. The receiver is to estimate a first time for receiving a signal, wherein the signal is associated with a synchronization operation. The receiver is further to receive the signal at a second time. The receiver is further to determine a difference between the second time and the first time, wherein the difference is associated with an error of the timestamp generator of the receiver. The receiver can also adjust the first rate to a second rate at which to update the timestamps by the timestamp generator, responsive to determining the difference between the first time and the second time.
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公开(公告)号：US11762785B2
公开(公告)日：2023-09-19
申请号：US17306033
申请日：2021-05-03
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Idan Burstein , Ilan Pardo , Yamin Friedman , Michael Cotsford , Mark Rosenbluth , Hillel Chapman
CPC classification number: G06F13/1668 , G06F12/0246 , G06F12/0811 , G06F13/382 , G06F13/4221 , G06F15/7807 , G06F2213/0026
Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.
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Patent Agency Ranking
公开(公告)号：US11711158B2
公开(公告)日：2023-07-25
申请号：US17359667
申请日：2021-06-28
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Dotan David Levi , Wojciech Wasko , Natan Manevich , Hillel Chapman , Roi Geuli , Eyal Serbro
IPC: H04J3/06
CPC classification number: H04J3/0661 , H04J3/062
Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.
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公开(公告)号：US20220078043A1
公开(公告)日：2022-03-10
申请号：US17013677
申请日：2020-09-07
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Daniel Marcovitch , Idan Burstein , Liran Liss , Hillel Chapman , Dror Goldenberg , Michael Kagan , Aviad Yehezkel , Peter Paneah
IPC: H04L12/46 , G06F13/42 , G06F13/40 , G06F15/173
Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.
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公开(公告)号：US10382350B2
公开(公告)日：2019-08-13
申请号：US15701459
申请日：2017-09-12
Applicant: Mellanox Technologies, Ltd.
Inventor： Dror Bohrer , Noam Bloch , Lior Narkis , Hillel Chapman , Gilad Hammer
IPC: G06F9/455 , H04L12/741 , H04L12/813 , H04L12/863 , H04L12/931
Abstract: Network interface apparatus includes a host interface and a network interface, which receives packets in multiple packet flows destined for one or more virtual machines running on a host processor. Packet processing circuitry receives a first instruction from the host processor to offload preprocessing of the data packets in a specified flow in accordance with a specified rule, and initiates preprocessing of the data packets while writing one or more initial data packets from the specified flow to a temporary buffer. Upon subsequently receiving a second instruction to enable the specified rule, the initial data packets are delivered from the temporary buffer, after preprocessing by the packet processing circuitry, directly to a virtual machine to which the specified flow is destined, followed by preprocessing and delivery of subsequent data packets in the specified flow to the virtual machine.
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公开(公告)号：US10158702B2
公开(公告)日：2018-12-18
申请号：US14937907
申请日：2015-11-11
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Noam Bloch , Gil Bloch , Ariel Shahar , Hillel Chapman , Gilad Shainer , Adi Menachem , Ofer Hayut
Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more work requests that are derived from an operation to be executed by the node. The NI maintains a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the work requests via the host interface, and to execute the work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.
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公开(公告)号：US10015090B2
公开(公告)日：2018-07-03
申请号：US15145848
申请日：2016-05-04
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Nir Haim Arad , Noam Bloch , Ariel Shahar , Hillel Chapman , Amir Wated
IPC: H04L12/741 , H04L12/931 , H04L12/721 , H04L12/801
CPC classification number: H04L45/74 , H04L45/38 , H04L45/745 , H04L47/10 , H04L49/351 , H04L49/355 , H04L49/358 , H04L49/70
Abstract: A method for steering packets includes receiving a packet and determining parameters to be used in steering the packet to a specific destination, in one or more initial steering stages, based on one or more packet specific attributes. The method further includes determining an identity of the specific destination of the packet in one or more subsequent steering stages, governed by the parameters determined in the one or more initial stages and one or more packet specific attributes, and forwarding the packet to the determined specific destination.
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