公开(公告)号：US20150029853A1

公开(公告)日：2015-01-29

申请号：US14338488

申请日：2014-07-23

Applicant: Mellanox Technologies Ltd.

Inventor： Shachar Raindel ,  Noam Bloch ,  Liran Liss ,  Diego Crupnicoff ,  Marina Lipshteyn

IPC: H04L12/801 ,  H04L12/851 ,  H04L12/931

CPC classification number: H04L47/127 ,  G06F3/0662 ,  G06F3/0664 ,  H04L12/4633 ,  H04L47/2441 ,  H04L49/50 ,  H04L49/70

Abstract: In a data network congestion control in a virtualized environment is enforced in packet flows to and from virtual machines in a host. A hypervisor and network interface hardware in the host are trusted components. Enforcement comprises estimating congestion states in the data network attributable to respective packet flows, recognizing a new packet that belongs to one of the data packet flows, and using one or more of the trusted components and to make a determination based on the congestion states that the new packet belongs to a congestion-producing packet flow. A congestion-control policy is applied by one or more of the trusted components to the new packet responsively to the determination.

Abstract translation: 在数据网络中，虚拟化环境中的拥塞控制在来自主机中的虚拟机的数据包流中实施。 主机中的管理程序和网络接口硬件是可信组件。 执行包括估计可归因于相应分组流的数据网络中的拥塞状态，识别属于数据分组流之一的新分组，以及使用一个或多个可信组件，并基于拥塞状态进行确定 新分组属于产生拥塞的分组流。 响应于该确定，拥塞控制策略由一个或多个可信任组件应用于新分组。

公开(公告)号：US20140324939A1

公开(公告)日：2014-10-30

申请号：US14324246

申请日：2014-07-07

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Noam Bloch ,  Gil Bloch ,  Ariel Shachar ,  Hillel Chapman ,  Ishai Rabinobitz ,  Pavel Shamis ,  Gilad Shainer

IPC: H04L29/08

CPC classification number: H04L67/10 ,  G06F9/546 ,  G06F2209/509

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract translation: 网络接口（NI）包括主机接口，其被配置为从节点的主机处理器接收从要由节点执行的操作导出的一个或多个跨通道工作请求。 NI包括用于通过网络向一个或多个对等节点执行传输信道的多个工作队列。 NI还包括控制电路，其被配置为经由主机接口接受跨通道工作请求，并且通过根据一个或多个控制电路控制至少一个给定的工作队列的前进来执行使用工作队列的跨通道工作请求 这取决于一个或多个其他工作队列的完成状态，以便执行操作。

公开(公告)号：US20140185616A1

公开(公告)日：2014-07-03

申请号：US13731130

申请日：2012-12-31

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Noam Bloch ,  Eitan Hirshberg ,  Michael Kagan

IPC: H04L12/56

CPC classification number: H04L67/10 ,  G06F9/45533 ,  H04L12/4633 ,  H04L45/64

Abstract: A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.

Abstract translation: 网络接口设备包括用于连接到具有存储器的主机处理器的主机接口。 网络接口被配置为通过数据网络发送和接收数据分组，数据网络支持覆盖在数据网络上的多个租户网络。 处理电路被配置为经由主机接口接收由主机处理器上运行的虚拟机提交的工作项，并且响应于工作项识别虚拟机被授权通信的租户网络，其中 工作项目指定要发送到租户目标地址的消息。 处理电路响应于工作项产生包含与租户网络相关联的封装头部的数据分组，并且通过数据网络将数据分组发送到与指定的租户目的地对应的至少一个数据网络地址 地址。

公开(公告)号：US20140122828A1

公开(公告)日：2014-05-01

申请号：US13665946

申请日：2012-11-01

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Michael Kagan ,  Noam Bloch ,  Liran Liss ,  Shachar Raindel

IPC: G06F12/10

CPC classification number: G06F12/1081

Abstract: A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory.

Abstract translation: 一种用于存储器访问的方法包括在主机操作系统在中央处理单元（CPU）上运行的主机操作系统的控制下维护主机存储器，用于由CPU执行的多个进程的各自的地址转换表。 在外围设备中接收与给定进程相关联的工作项，在主机存储器中具有相应的地址转换表，并指定虚拟存储器地址时，外围设备将虚拟存储器地址转换为物理存储器地址 通过访问主机存储器中给定进程的相应地址转换表。 通过访问主机存储器中的物理存储器地址上的数据，在外围设备中执行工作项。

公开(公告)号：US12058309B2

公开(公告)日：2024-08-06

申请号：US16291023

申请日：2019-03-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Assaf Weissman ,  Kobi Pines ,  Noam Bloch ,  Erez Yaacov ,  Ariel Naftali Cohen

IPC: H04N19/105 ,  H04N19/139 ,  H04N19/147 ,  H04N19/176

CPC classification number: H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/147

Abstract: A system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each the block of the second plurality of blocks, to produce a score of result blocks based on similarity of each the block in each frame to be encoded to every block of the reference frame, and a displacement vector. Related apparatus and methods are also provided.

公开(公告)号：US20240193106A1

公开(公告)日：2024-06-13

申请号：US18444804

申请日：2024-02-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F9/455 ,  G06F9/46 ,  G06F12/1045 ,  G06F13/38 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F13/1668 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/387 ,  G06F13/4221 ,  G06F15/17331 ,  G06F2009/45579

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US20240143527A1

公开(公告)日：2024-05-02

申请号：US17977910

申请日：2022-10-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Daniel Marcovitch ,  Roman Nudelman ,  Noam Bloch

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F13/1668 ,  G06F2213/0026 ,  G06F2213/3808

Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.

公开(公告)号：US11940933B2

公开(公告)日：2024-03-26

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F9/455 ,  G06F9/46 ,  G06F12/1045 ,  G06F13/38 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F13/1668 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/387 ,  G06F13/4221 ,  G06F15/17331 ,  G06F2009/45579

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US20230214341A1

公开(公告)日：2023-07-06

申请号：US18174668

申请日：2023-02-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

IPC: G06F13/28 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0673 ,  G06F2213/28

Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

公开(公告)号：US11558175B2

公开(公告)日：2023-01-17

申请号：US17233591

申请日：2021-04-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32

Abstract: In one embodiment, data communication apparatus includes a network interface for connection to a network and configured to receive a sequence of data packets from a remote device over the network, the sequence including data blocks, ones of the data blocks having block boundaries that are not aligned with payload boundaries of the packets, and packet processing circuitry to cryptographically process the data blocks using a block cipher so as to write corresponding cryptographically processed data blocks to a memory, while holding segments of respective ones of the received data blocks in the memory, such that the packet processing circuitry stores a first segment of a data block of a first packet in the memory until a second packet is received, and then cryptographically processes the first and second segments together so as to write a corresponding cryptographically processed data block to the memory.