公开(公告)号：US20240164114A1

公开(公告)日：2024-05-16

申请号：US18522637

申请日：2023-11-29

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H10B53/20 ,  H01L21/223 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

CPC classification number: H10B53/20 ,  H01L21/223 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US11862668B2

公开(公告)日：2024-01-02

申请号：US17366557

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan ,  Manuj Nahar

IPC: H01L29/04 ,  H01L29/10 ,  H10B12/00 ,  H10B53/30

CPC classification number: H01L29/04 ,  H01L29/1033 ,  H10B12/00 ,  H10B53/30

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

公开(公告)号：US20200066516A1

公开(公告)日：2020-02-27

申请号：US16112372

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Darwin Franseda Fan

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/108 ,  C30B25/18 ,  C30B29/06 ,  C30B29/08

Abstract: Some embodiments include a semiconductor structure having a laminate which has first regions alternating with second regions. The first regions include silicon, and the second regions include germanium. Some embodiments include a method of forming a semiconductor structure. The semiconductor structure may correspond to at least a portion of an active region of a transistor. A first semiconductor material is deposited with a first deposition process. The first semiconductor material includes silicon. The first deposition process is intermittently interrupted to etch a surface of the deposited first semiconductor material and to deposit a second semiconductor material with a second deposition process. The second semiconductor material includes germanium. The semiconductor structure is at least partially crystalline.

公开(公告)号：US10170639B2

公开(公告)日：2019-01-01

申请号：US14987147

申请日：2016-01-04

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11556 ,  H01L29/40 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/51 ,  H01L27/11524 ,  H01L29/78

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

公开(公告)号：US20170200801A1

公开(公告)日：2017-07-13

申请号：US15470617

申请日：2017-03-27

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Darwin Franseda Fan

IPC: H01L29/49 ,  H01L21/311 ,  H01L29/423 ,  H01L27/11556 ,  H01L21/02 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L29/4916 ,  H01L27/11556 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/7883

Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

公开(公告)号：US20230006034A1

公开(公告)日：2023-01-05

申请号：US17366557

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Masihhur R. Laskar ,  Nicholas R. Tapias ,  Darwin Franseda Fan

IPC: H01L29/04 ,  H01L29/10

Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

公开(公告)号：US20220238417A1

公开(公告)日：2022-07-28

申请号：US17721919

申请日：2022-04-15

Applicant: Micron Technology, Inc.

Inventor： Zhuo Chen ,  Irina V. Vasilyeva ,  Darwin Franseda Fan ,  Kamal Kumar Muthukrishnan

IPC: H01L23/48 ,  H01L27/108 ,  H01L27/11504 ,  H01L21/48 ,  H01L27/11507 ,  H01L27/11509

Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

公开(公告)号：US11335626B2

公开(公告)日：2022-05-17

申请号：US17021793

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Zhuo Chen ,  Irina V. Vasilyeva ,  Darwin Franseda Fan ,  Kamal Kumar Muthukrishnan

IPC: H01L23/48 ,  H01L27/108 ,  H01L27/11504 ,  H01L21/48 ,  H01L27/11507 ,  H01L27/11509

Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

公开(公告)号：US20220084906A1

公开(公告)日：2022-03-17

申请号：US17021793

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Zhuo Chen ,  Irina V. Vasilyeva ,  Darwin Franseda Fan ,  Kamal Kumar Muthukrishnan

IPC: H01L23/48 ,  H01L27/108 ,  H01L27/11504 ,  H01L27/11509 ,  H01L27/11507 ,  H01L21/48

Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

公开(公告)号：US20210043768A1

公开(公告)日：2021-02-11

申请号：US16536479

申请日：2019-08-09

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Darwin Franseda Fan ,  Ali Moballegh

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/04 ,  H01L21/02 ,  H01L29/66

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.