公开(公告)号：US20180130700A1

公开(公告)日：2018-05-10

申请号：US15867017

申请日：2018-01-10

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/033 ,  H01L27/105 ,  H01L23/535

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76822 ,  H01L21/76865 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

公开(公告)号：US09870941B2

公开(公告)日：2018-01-16

申请号：US15359218

申请日：2016-11-22

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

IPC: H01L29/792 ,  H01L21/768 ,  H01L27/105 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/11548 ,  H01L27/11575

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76822 ,  H01L21/76865 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

公开(公告)号：US20170076977A1

公开(公告)日：2017-03-16

申请号：US15359218

申请日：2016-11-22

Applicant: Micron Technology, Inc.

Inventor： Chang Wan Ha ,  Graham R. Wolstenholme ,  Deepak Thimmegowda

IPC: H01L21/768 ,  H01L21/3213 ,  H01L27/105

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76822 ,  H01L21/76865 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Abstract translation: 提供了使用至少两个掩模（例如存储器件）中的阶梯形成的装置和方法。 一个示例性方法可以包括在导电材料上形成第一掩模以限定第一暴露区域，以及在第一暴露区域的一部分上形成第二掩模以限定第二暴露区域，第二暴露区域小于第一暴露区域 区。 从第二暴露区域去除导电材料。 第二掩模的初始第一尺寸小于第一曝光区域的第一尺寸，并且第二掩模的初始第二尺寸是第一曝光区域的至少第二尺寸加上等于初始第一曝光区域之间的差距的距离 在形成阶梯结构之后，第二掩模的尺寸和第二掩模的最终第一尺寸。

公开(公告)号：US20160195581A1

公开(公告)日：2016-07-07

申请号：US15069316

申请日：2016-03-14

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Kenneth W. Marr ,  Deepak Thimmegowda ,  Philip J. Ireland

IPC: G01R31/28

CPC classification number: G01R31/2896 ,  H01L22/14 ,  H01L22/34 ,  H01L23/48 ,  H01L23/481 ,  H01L23/485 ,  H01L29/7823 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.

公开(公告)号：US20160079274A1

公开(公告)日：2016-03-17

申请号：US14949778

申请日：2015-11-23

Applicant: Micron Technology, Inc.

Inventor： Deepak Thimmegowda ,  Andrew R. Bicksler ,  Roland Awusie

IPC: H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/66 ,  H01L29/792 ,  H01L29/49 ,  H01L21/283

CPC classification number: H01L27/11524 ,  H01L21/28035 ,  H01L21/28097 ,  H01L21/283 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/4925 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7828 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

公开(公告)号：US09219132B2

公开(公告)日：2015-12-22

申请号：US14491830

申请日：2014-09-19

Applicant: Micron Technology, Inc.

Inventor： Deepak Thimmegowda ,  Andrew R. Bicksler ,  Roland Awusie

IPC: H01L21/3205 ,  H01L21/44 ,  H01L21/30 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/16 ,  H01L29/49 ,  H01L27/115

CPC classification number: H01L27/11524 ,  H01L21/28035 ,  H01L21/28097 ,  H01L21/283 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/4925 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7828 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

Abstract translation: 一些实施例包括具有沿通道区域的第一段的第一导电栅极部分和沿着沟道区域的第二部分的第二导电栅极部分的晶体管。 第二导电栅极部分是与第一导电栅极部分不同的组成。 一些实施例包括形成半导体结构的方法。 第一半导体材料和含金属材料形成在NAND串上。 通过含金属材料和第一半导体材料形成开口，并且衬有栅极电介质。 第二半导体材料设置在开口内以形成晶体管的沟道区。 晶体管是电耦合到NAND串的选择器件。

公开(公告)号：US20150044834A1

公开(公告)日：2015-02-12

申请号：US14491830

申请日：2014-09-19

Applicant: Micron Technology, Inc.

Inventor： Deepak Thimmegowda ,  Andrew R. Bicksler ,  Roland Awusie

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/16

CPC classification number: H01L27/11524 ,  H01L21/28035 ,  H01L21/28097 ,  H01L21/283 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/4925 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7828 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

Abstract translation: 一些实施例包括具有沿通道区域的第一段的第一导电栅极部分和沿着沟道区域的第二部分的第二导电栅极部分的晶体管。 第二导电栅极部分是与第一导电栅极部分不同的组成。 一些实施例包括形成半导体结构的方法。 第一半导体材料和含金属材料形成在NAND串上。 通过含金属材料和第一半导体材料形成开口，并且衬有栅极电介质。 第二半导体材料设置在开口内以形成晶体管的沟道区。 晶体管是电耦合到NAND串的选择器件。

公开(公告)号：US20140217488A1

公开(公告)日：2014-08-07

申请号：US13759627

申请日：2013-02-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Deepak Thimmegowda ,  Brian Cleereman ,  Khaled Hasnat

IPC: H01L29/78

CPC classification number: H01L27/11556 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.

Abstract translation: 3-D存储器阵列包括多个高度延伸的存储器单元串。 选择装置的阵列是垂直于多个单独的弦与单独的连接。 选择装置分别包括通道，靠近通道的栅极电介质和靠近栅极电介质的栅极材料。 各个通道彼此间隔开。 栅极材料包括多个栅极线，这些栅极线沿垂直于串的间隔通道的列延伸。 介电材料横向位于紧邻栅极线之间。 介电材料和栅极线在界面处彼此具有纵向非线性边缘。 公开了另外的实施例。

公开(公告)号：US20140191340A1

公开(公告)日：2014-07-10

申请号：US13738147

申请日：2013-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Deepak Thimmegowda ,  Andrew R. Bicksler ,  Roland Awusie

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11524 ,  H01L21/28035 ,  H01L21/28097 ,  H01L21/283 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/4925 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7828 ,  H01L29/7889 ,  H01L29/7926

Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

Abstract translation: 一些实施例包括具有沿通道区域的第一段的第一导电栅极部分和沿着沟道区域的第二部分的第二导电栅极部分的晶体管。 第二导电栅极部分是与第一导电栅极部分不同的组成。 一些实施例包括形成半导体结构的方法。 第一半导体材料和含金属材料形成在NAND串上。 通过含金属材料和第一半导体材料形成开口，并且衬有栅极电介质。 第二半导体材料设置在开口内以形成晶体管的沟道区。 晶体管是电耦合到NAND串的选择器件。