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公开(公告)号：US20150286585A1
公开(公告)日：2015-10-08
申请号：US14677712
申请日：2015-04-02
Applicant: Micron Technology, Inc.
Inventor： Danilo Caraccio , Graziano Mirichigni
IPC: G06F12/14
CPC classification number: G06F12/1458 , G06F12/1408 , G06F21/79 , G06F2212/1052
Abstract: A device includes a memory. The device also includes a controller. The controller includes a register configured to store an indication of whether an ability of a received command to alter an access protection scheme of the memory is enabled. The received command may alter the access an access protection scheme of the memory responsive to the indication.
Abstract translation: 设备包括存储器。 该设备还包括一个控制器。 所述控制器包括：寄存器，被配置为存储所接收的命令是否能够改变所述存储器的访问保护方案的能力的指示。 接收到的命令可以响应于该指示而改变对存储器的访问保护方案的访问。
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公开(公告)号：US20140369138A1
公开(公告)日：2014-12-18
申请号：US14472003
申请日：2014-08-28
Applicant: Micron Technology, Inc.
Inventor： Daniele Balluchi , Graziano Mirichigni
IPC: G11C7/10
CPC classification number: G06F3/0604 , G06F3/0629 , G06F3/0685 , G06F12/0638 , G06F2212/2022 , G11C7/1015 , G11C7/1078 , G11C7/1084 , G11C16/102 , G11C16/32 , Y02D10/13
Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.
Abstract translation: 非易失性存储器件包括：第一缓冲寄存器，用于接收和存储要存储到经由存储器总线提供的存储器件中的数据。 命令窗口可激活以插入其自身以访问第一缓冲元件和存储器矩阵之间的存储器矩阵。 命令窗口包括第二缓冲器元件，其存储存储在存储器或存储到一组存储器元件中的数据。 在通过接收第一命令开始的数据写入操作的第一阶段期间，第一数据传送装置执行将存储在第二缓冲寄存器中的数据的第一传送到第一缓冲寄存器。 第二数据传送装置接收由存储器总线提供的数据，并且在通过接收第二命令开始的数据写入操作的第二阶段期间，基于接收的数据修改存储在第一缓冲寄存器中的数据。 第一传送装置在数据写入操作的第三阶段期间执行将存储在第一缓冲寄存器中的修改数据的第二传送到第二缓冲寄存器。 响应于与第二命令一起接收由存储器总线接收的信号执行第二传送。
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23.发明申请公开(公告)号：US20140068380A1
公开(公告)日：2014-03-06
申请号：US14074360
申请日：2013-11-07
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni
IPC: G06F11/10
CPC classification number: G06F11/1048 , G06F11/1016 , G06F11/1044 , G06F11/1072 , G06F11/1096 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C29/52 , G11C2211/5623 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/2909 , H03M13/6561
Abstract: Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a response to a read request of contents of the particular partition may be delayed. In some embodiments, the contents of the particular partition may be indirectly read during the write process without delaying the response to the read request. The contents of the particular partition can be indirectly read by determining the contents of the particular partition based, at least in part, on an error correction code based, at least in part, on contents of memory partitions of the memory array.
Abstract translation: 本文公开的主题涉及存储器件的读取和写入过程。 在对存储器阵列中的特定分区的写入处理期间，可能延迟对特定分区的内容的读取请求的响应。 在一些实施例中，特定分区的内容可以在写入过程期间间接读取，而不会延迟对读请求的响应。 至少部分地基于至少部分地基于存储器阵列的存储器分区的内容的纠错码来确定特定分区的内容来间接读取特定分区的内容。
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公开(公告)号：US20140022854A1
公开(公告)日：2014-01-23
申请号：US14034275
申请日：2013-09-23
Applicant: Micron Technology, Inc.
Inventor： Daniele Balluchi , Graziano Mirichigni
IPC: G11C7/10
CPC classification number: G06F3/0604 , G06F3/0629 , G06F3/0685 , G06F12/0638 , G06F2212/2022 , G11C7/1015 , G11C7/1078 , G11C7/1084 , G11C16/102 , G11C16/32 , Y02D10/13
Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.
Abstract translation: 非易失性存储器件包括：第一缓冲寄存器，用于接收和存储要存储到经由存储器总线提供的存储器件中的数据。 命令窗口可激活以插入其自身以访问第一缓冲元件和存储器矩阵之间的存储器矩阵。 命令窗口包括第二缓冲器元件，其存储存储在存储器或存储到一组存储器元件中的数据。 在通过接收第一命令开始的数据写入操作的第一阶段期间，第一数据传送装置执行将存储在第二缓冲寄存器中的数据的第一传送到第一缓冲寄存器。 第二数据传送装置接收由存储器总线提供的数据，并且在通过接收第二命令开始的数据写入操作的第二阶段期间，基于接收的数据修改存储在第一缓冲寄存器中的数据。 第一传送装置在数据写入操作的第三阶段期间执行将存储在第一缓冲寄存器中的修改数据的第二传送到第二缓冲寄存器。 响应于与第二命令一起接收由存储器总线接收的信号执行第二传送。
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公开(公告)号：US20250130718A1
公开(公告)日：2025-04-24
申请号：US18889047
申请日：2024-09-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Antonino Caprì , Graziano Mirichigni , Marco Sforzin , Bryan David Kerstetter , John David Porter
IPC: G06F3/06
Abstract: A system performs operations including: storing a first value in a first memory location used for selecting a sub-channel of a plurality of sub-channels in a communication channel, each of the plurality of sub-channels corresponding to one or more memory components of a plurality of memory components of the memory device, wherein the first value specifies that a sub-channel selecting function is enabled; receiving, through the communication channel, a command directed to the memory device; responsive to receiving the command, storing a second value in a second memory location, wherein the second value is obtained from the command; determining that the second value matches a third value stored in a third memory location, wherein the third value stored in the third memory location comprises a preset value corresponding to a first component of the plurality of components of the memory device; and executing, by the first component, the command.
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Patent Agency Ranking
公开(公告)号：US20240353914A1
公开(公告)日：2024-10-24
申请号：US18762482
申请日：2024-07-02
Applicant: Micron Technology, Inc.
IPC: G06F1/3287 , G06F1/28 , G06F1/3234 , G11C11/22 , G11C11/4096
CPC classification number: G06F1/3287 , G06F1/28 , G06F1/3275 , G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/4096
Abstract: Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.
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公开(公告)号：US12045113B2
公开(公告)日：2024-07-23
申请号：US16551581
申请日：2019-08-26
Applicant: Micron Technology, Inc.
IPC: G06F1/3287 , G06F1/28 , G06F1/3234 , G11C11/22 , G11C11/4096
CPC classification number: G06F1/3287 , G06F1/28 , G06F1/3275 , G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/4096
Abstract: Methods, systems, and devices for bank-configurable power modes are described. Aspects include operating a memory device that has multiple memory banks in a first mode. While operating in the first mode, the memory device may receive a command to enter a second mode having a lower power consumption level than the first mode. The memory device may enter the second mode by switching a first subset of the memory banks to a first low power mode that operates at a first power consumption level and a second subset of the memory banks to a second low power mode that operates at a second power consumption level that may be lower than the first power consumption level. In some cases, the memory device may switch the first subset of memory banks from the first low power mode while maintaining the second subset of memory banks in the low power mode.
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公开(公告)号：US20240221798A1
公开(公告)日：2024-07-04
申请号：US18408228
申请日：2024-01-09
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Efrem Bolandrina
CPC classification number: G11C7/1063 , G11C7/1048 , G11C7/109 , G11C8/18
Abstract: Methods, systems, and devices for techniques for indicating row activation are described. A memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. The indication may include a location of a next row to access as part of the activation command. The indication may be included in a previous activation command or in a precharge command. The memory device may begin activation operations for the next row before the precharge operation of the current row is complete. The memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.
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公开(公告)号：US11887664B2
公开(公告)日：2024-01-30
申请号：US18079515
申请日：2022-12-12
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Corrado Villa
CPC classification number: G11C13/004 , G11C13/0026 , G11C13/0028 , G11C2013/0045
Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.
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公开(公告)号：US11282571B2
公开(公告)日：2022-03-22
申请号：US17165579
申请日：2021-02-02
Applicant: Micron Technology, Inc.
Inventor： Graziano Mirichigni , Marco Sforzin , Alessandro Orlando
Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage. When the time duration expires, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.
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