公开(公告)号：US20210066247A1

公开(公告)日：2021-03-04

申请号：US16553549

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa ,  Raj K. Bansal ,  Shunji Kuwahara ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  G11C11/4096

Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

公开(公告)号：US20180358064A1

公开(公告)日：2018-12-13

申请号：US16107909

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Shuichi Ishibashi ,  Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C8/18 ,  G11C7/10 ,  G11C29/02 ,  G11C11/4076

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

公开(公告)号：US20170309323A1

公开(公告)日：2017-10-26

申请号：US15595056

申请日：2017-05-15

Applicant: Micron Technology, Inc.

Inventor： Shuichi Ishibashi ,  Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C11/4076 ,  G11C7/22 ,  G11C7/10 ,  G11C8/10

CPC classification number: G11C8/18 ,  G11C7/1015 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/10 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/024 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

公开(公告)号：US20170229165A1

公开(公告)日：2017-08-10

申请号：US15499568

申请日：2017-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KENJI YOSHIDA ,  Hiroki Fujisawa

IPC: G11C11/406 ,  G11C11/4094

CPC classification number: G11C11/40626 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2211/4061

Abstract: Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command: and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle, to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.

公开(公告)号：US09406606B2

公开(公告)日：2016-08-02

申请号：US14336984

申请日：2014-07-21

Applicant: Micron Technology, Inc.

Inventor： Hiroki Fujisawa

IPC: G11C17/00 ,  H01L23/525 ,  G11C29/00 ,  G11C17/16 ,  H01L23/528

CPC classification number: H01L23/5252 ,  G11C17/16 ,  G11C29/789 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other.

Abstract translation: 一种设备包括：第一电源线，用于提供第一电压，第一，第二和第三节点，连接在第一电源线和第一节点之间的选择电路，连接在第一节点和第二节点之间的第一反熔丝 以及连接在第一节点和第三节点之间的第二反熔丝。 第二节点和第三节点没有彼此连接。

公开(公告)号：US09196349B2

公开(公告)日：2015-11-24

申请号：US14341601

申请日：2014-07-25

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C8/00 ,  G11C11/4074 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C11/4074 ,  G11C7/1057 ,  G11C7/222 ,  G11C2207/2227

Abstract: A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.

Abstract translation: 一种设备包括输出电路，DLL（延迟锁定环路）电路，包括接收第一时钟信号的第一延迟线，并且响应于接收到时钟信号而输出提供给输出电路的第二时钟信号，以及ODT 接通ODT激活信号，并且响应于接收到ODT激活信号而输出提供给输出电路的ODT输出信号，以将输出电路设置为电阻终止状态，并且包括第二延迟的ODT电路 线路被配置为由等效延迟量等效于第一延迟线的延迟量由DLL电路设置，ODT输出信号在ODT激活信号处于活动状态的第一时间段期间 通过被设置了等效延迟量的第二延迟线传送而产生。

公开(公告)号：US20150255145A1

公开(公告)日：2015-09-10

申请号：US14638836

申请日：2015-03-04

Applicant: Micron Technology, Inc.

Inventor： Hiroto Kinoshita ,  Hiroki Fujisawa

IPC: G11C11/408

CPC classification number: G11C11/4082 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4093 ,  G11C2207/105

Abstract: A device includes a plurality of input terminals, a control circuit, and a plurality of signal buses. Each of the signal buses is coupled between the control circuit and an associated one of the plurality of input terminals and includes one or more first buffers, one or more second buffers and at least one latch circuit coupled between the one or more first buffers and the one or more second buffers. The one or more first buffers of one of the signal buses are different in number from the one or more first buffers of a different one of the signal buses.

Abstract translation: 一种装置包括多个输入端子，一个控制电路和多个信号总线。 信号总线中的每一个耦合在控制电路和多个输入终端中相关联的一个之间，并且包括一个或多个第一缓冲器，一个或多个第二缓冲器和耦合在一个或多个第一缓冲器和 一个或多个第二缓冲器。 一个信号总线的一个或多个第一缓冲器的数量与不同信号总线的一个或多个第一缓冲器不同。

公开(公告)号：US20150120997A1

公开(公告)日：2015-04-30

申请号：US14523704

申请日：2014-10-24

Applicant: Micron Technology, Inc.

Inventor： SHINGO MITSUBORI ,  Hiroki Fujisawa

IPC: G11C7/10

CPC classification number: G11C5/025 ,  G11C7/08 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

Abstract: A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from the first memory cell array, a second main data line that transfers the read data read from the second memory cell array, a main amplifier coupled to the second main data line, and a repeater circuit coupled to the first main data line and the second main data line.

Abstract translation: 本公开中公开的半导体存储器包括第一和第二存储器单元阵列，传送从第一存储单元阵列读取的读取数据的第一主数据线，传送从第二存储单元阵列读取的读取数据的第二主数据线 耦合到第二主数据线的主放大器，以及耦合到第一主数据线和第二主数据线的中继器电路。

公开(公告)号：US10290336B2

公开(公告)日：2019-05-14

申请号：US15595056

申请日：2017-05-15

Applicant: Micron Technology, Inc.

Inventor： Shuichi Ishibashi ,  Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C11/4076 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/02

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

公开(公告)号：US20180047438A1

公开(公告)日：2018-02-15

申请号：US15729345

申请日：2017-10-10

Applicant: Micron Technology, Inc.

Inventor： HIROMASA TAKEDA ,  Hiroki Fujisawa

IPC: G11C11/4093 ,  G11C11/4074 ,  G11C11/4094 ,  G11C7/10

CPC classification number: G11C11/4093 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/4074 ,  G11C11/4094 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

Abstract: An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.