公开(公告)号：US11886726B2

公开(公告)日：2024-01-30

申请号：US17542943

申请日：2021-12-06

申请人： Micron Technology, Inc.

发明人： Michael Sheperek ,  Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu ,  Bruce A. Liikanen ,  Peter Feeley ,  Larry J. Koudele ,  Shane Nowell ,  Steven Michael Kientz

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/10 ,  G11C16/26 ,  G11C16/04

CPC分类号： G06F3/064 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/10 ,  G11C16/26 ,  G06F2212/1041 ,  G11C16/0483

摘要： An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

公开(公告)号：US11823722B2

公开(公告)日：2023-11-21

申请号：US18110008

申请日：2023-02-15

申请人： MICRON TECHNOLOGY, INC.

发明人： Kishore Kumar Muchherla ,  Mustafa N Kaynak ,  Sampath K Ratnam ,  Shane Nowell ,  Peter Feeley ,  Sivagnanam Parthasarathy

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/32 ,  G11C16/26

CPC分类号： G11C16/3404 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

摘要： A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.

公开(公告)号：US11726689B2

公开(公告)日：2023-08-15

申请号：US17100712

申请日：2020-11-20

申请人： MICRON TECHNOLOGY, INC.

发明人： Shane Nowell ,  Michael Sheperek ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC分类号： G06F3/06

CPC分类号： G06F3/064 ,  G06F3/0604 ,  G06F3/0614 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

摘要： An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to determine that a first block family of a plurality of block families of the memory device and a second block family of the plurality of block families satisfy a proximity condition; determine whether the first block family and the second block family meet a time-based combining criterion corresponding to the proximity condition; and responsive to determining that the first block family and the second block family meet the time-based combining criterion, merge the first block family and the second block family.

公开(公告)号：US11704217B2

公开(公告)日：2023-07-18

申请号：US17157220

申请日：2021-01-25

申请人： Micron Technology, Inc.

发明人： Michael Sheperek ,  Steven Michael Kientz ,  Shane Nowell ,  Mustafa N. Kaynak ,  Kishore Kumar Muchherla ,  Larry J. Koudele

IPC分类号： G06F11/30 ,  G06F3/06 ,  G06F11/07

CPC分类号： G06F11/3037 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/3058

摘要： A memory system includes a memory device and a processing device, operatively coupled to the memory device. The processing device performs operations comprising: identifying an operating temperature of the memory device; determining that the operating temperature satisfies a temperature condition; modifying a scan frequency parameter for performing a scan operation on representative blocks of a set of blocks in the memory device; and performing the scan operation at a frequency identified by the scan frequency parameter.

公开(公告)号：US11693745B2

公开(公告)日：2023-07-04

申请号：US17102272

申请日：2020-11-23

申请人： MICRON TECHNOLOGY, INC.

发明人： Bruce A. Liikanen ,  Shane Nowell ,  Steven Michael Kientz

IPC分类号： G06F11/20 ,  H03M13/09 ,  G11C16/34 ,  G06F1/26

CPC分类号： G06F11/2002 ,  G06F1/26 ,  G11C16/3436 ,  H03M13/09 ,  G06F2201/85

摘要： An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to detect a power-up state of the memory device following a power loss event; detect a read error with respect to data residing in a block of the memory device, wherein the block is associated with a current voltage offset bin; and perform temporal voltage shift (TVS)-oriented calibration for associating the block with a new voltage offset bin.

公开(公告)号：US20230205447A1

公开(公告)日：2023-06-29

申请号：US18175439

申请日：2023-02-27

申请人： MICRON TECHNOLOGY, INC.

发明人： Kishore Kumar Muchherla ,  Devin M. Batutis ,  Xiangang Luo ,  Mustafa N. Kaynak ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Sampath Ratnam ,  Shane Nowell

IPC分类号： G06F3/06

CPC分类号： G06F3/0653 ,  G06F3/0679 ,  G06F3/0604 ,  G06F3/0655

摘要： A current value for a reference voltage for a block family is determined. An amount of voltage shift for a memory page of the block family is determined based on the current value for the reference voltage and a prior value for the reference voltage. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

公开(公告)号：US11675529B2

公开(公告)日：2023-06-13

申请号：US17233317

申请日：2021-04-16

申请人： MICRON TECHNOLOGY, INC.

发明人： Kishore Kumar Muchherla ,  Sampath K Ratnam ,  Shane Nowell ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Mustafa N Kaynak

IPC分类号： G06F3/00 ,  G06F3/06

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0679

摘要： A processing device of a memory sub-system is configured to identify a plurality of blocks assigned to a first voltage bin of a plurality of voltage bins of a memory device; identify a subset of the plurality of blocks having a time after program (TAP) within a predetermined threshold period of time from a second TAP associated with a transition boundary between the first voltage bin and a subsequent voltage bin of the plurality of voltage bins; determine a threshold voltage offset associated with the subset of blocks; and associate the threshold voltage offset with the subsequent voltage bin.

公开(公告)号：US11675509B2

公开(公告)日：2023-06-13

申请号：US17084540

申请日：2020-10-29

申请人： MICRON TECHNOLOGY, INC.

发明人： Shane Nowell ,  Michael Sheperek ,  Larry J Koudele ,  Bruce A Liikanen ,  Steve Kientz

IPC分类号： G06F3/06

CPC分类号： G06F3/064 ,  G06F3/0604 ,  G06F3/0688

摘要： An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to open a first block family associated with the memory device; assign a first cursor of a plurality of cursors of the memory device to the first block family; responsive to programming a first block associated with the first cursor, associate the first block with the first block family; open, while the first block family is open, a second block family associated with the memory device; assign a second cursor of the plurality of cursors of the memory device to the second block family; and responsive to programming a second block associated with the second cursor, associate the second block with the second block family.

公开(公告)号：US11593005B2

公开(公告)日：2023-02-28

申请号：US17219489

申请日：2021-03-31

申请人： MICRON TECHNOLOGY, INC.

发明人： Kishore Kumar Muchherla ,  Mustafa N Kaynak ,  Peter Feeley ,  Sampath K Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Karl D Schuh ,  Jiangang Wu

IPC分类号： G06F3/06 ,  G11C16/26

摘要： A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; divide the sorted plurality of blocks into a plurality of block segments; scan a first block at a first boundary of a first block segment of the plurality of block segments; scan a second block at a second boundary of the first block segment; identify, based on a scanning result of the first block, a first voltage bin associated with the first block; identify, based on a second scanning result of the second block, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block of a subset of the plurality of blocks assigned to the first block segment.

公开(公告)号：US11532373B2

公开(公告)日：2022-12-20

申请号：US17205091

申请日：2021-03-18

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Sampath K. Ratnam ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Devin M. Batutis ,  Xiangang Luo

IPC分类号： G11C29/42 ,  G11C16/26 ,  G11C29/44 ,  G11C16/10 ,  G11C29/12

摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block, and performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table.