中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

101 records (took 0.023 seconds)

    Multi-chip package, controlling method of multi-chip package and security chip
    21.
    发明申请
    Multi-chip package, controlling method of multi-chip package and security chip 审中-公开

    公开(公告)号：US20200057575A1

    公开(公告)日：2020-02-20

    申请号：US15998456

    申请日：2018-08-15

    Applicant: Macronix International Co., Ltd.

    Inventor： Chia-Jung Chen ,  Chin-Hung Chang ,  Ken-Hui Chen

    IPC: G06F3/06

    Abstract: A multi-chip package, a controlling method of the multi-chip package and a security chip are provided. The multi-chip package includes a memory chip and a security chip. The security chip is coupled between the memory chip and a host. The security chip includes a processing circuit. The processing circuit is for enabling a security path to input an input-output signal into the processing circuit for executing a security procedure and accessing the memory chip, if a command is received by the processing circuit and the command includes a security requirement.

    Memory and method for operating a memory with interruptible command sequence
    22.
    发明授权
    Memory and method for operating a memory with interruptible command sequence 有权

    公开(公告)号：US10289596B2

    公开(公告)日：2019-05-14

    申请号：US15411731

    申请日：2017-01-20

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Ken-Hui Chen ,  Kuen-Long Chang ,  Su-Chueh Lo ,  Chun-Yu Liao

    IPC: G06F13/42 ,  G06F13/16

    Abstract: A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.

    NESTED WRAP-AROUND MEMORY ACCESS
    24.
    发明申请
    NESTED WRAP-AROUND MEMORY ACCESS 审中-公开

    公开(公告)号：US20170308463A1

    公开(公告)日：2017-10-26

    申请号：US15139252

    申请日：2016-04-26

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F12/06

    CPC classification number: G06F12/0623 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/2022 ,  G11C16/08

    Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

    ECC method for double pattern flash memory
    25.
    发明授权
    ECC method for double pattern flash memory 有权

    公开(公告)号：US09760434B2

    公开(公告)日：2017-09-12

    申请号：US14841950

    申请日：2015-09-01

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shih-Chang Huang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F11/10 ,  G11C29/52 ,  G11C29/04

    CPC classification number: G06F11/1068 ,  G06F11/1052 ,  G11C29/52 ,  G11C2029/0411

    Abstract: A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC.

    Circuit with output switch
    27.
    发明授权
    Circuit with output switch 有权
    电路带输出开关

    公开(公告)号：US09450577B1

    公开(公告)日：2016-09-20

    申请号：US14742160

    申请日：2015-06-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Su-Chueh Lo ,  Tzu-Ting Chiu

    IPC: H03K3/00 ,  H03K17/16

    CPC classification number: H03K19/018507

    Abstract: An output circuit includes: an output switch including a gate terminal, a drain terminal coupled to an external I/O bus, and a well terminal; a well control circuit, having a well terminal coupled to the well terminal of the output switch, to maintain a well voltage of the output switch at a level not less than a greater of a first voltage and a second voltage; and a gate control circuit coupled to the gate terminal and a the drain terminal of the output switch and to the external I/O bus, and operable to turn off the output switch, to prevent current flow through the output switch from the external I/O bus when an operating voltage of the output circuit is not applied to the output switch, and a bus voltage from an external device is present on the external I/O bus.

    Abstract translation: 输出电路包括：输出开关，包括栅极端子，耦合到外部I / O总线的漏极端子和阱端子; 阱控制电路，具有耦合到输出开关的阱端子的阱端子，以将输出开关的阱电压保持在不小于第一电压和第二电压的较大值的水平; 以及栅极控制电路，其耦合到输出开关的栅极端子和漏极端子和外部I / O总线，并且可操作以关闭输出开关，以防止电流从外部I / O总线流过输出开关， O总线时，输出电路的工作电压不被施加到输出开关，并且来自外部设备的总线电压存在于外部I / O总线上。

    Stabilization of output timing delay
    28.
    发明授权
    Stabilization of output timing delay 有权
    稳定输出定时延时

    公开(公告)号：US09444462B2

    公开(公告)日：2016-09-13

    申请号：US14458936

    申请日：2014-08-13

    Applicant: Macronix International Co., Ltd.

    Inventor： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen

    IPC: H03K3/00 ,  H03K19/0185 ,  H03K19/003

    CPC classification number: H03K19/018521 ,  H03K19/00384

    Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. Alternatively, the output buffer delay is variable. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and can include a first delay circuit that generates the first timing signal with a first delay, and a second delay circuit that generates the second timing signal with a second delay that correlates with the output buffer delay.

    Abstract translation: 集成电路包括输出缓冲器和控制电路。 输出缓冲器具有信号输入，信号输出和一组控制输入。 输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。 或者，输出缓冲器延迟是可变的。 控制电路连接到输出缓冲器的一组控制输入。 控制电路使用第一和第二定时信号来产生控制信号，并且可以包括产生具有第一延迟的第一定时信号的第一延迟电路和产生具有第二延迟的第二定时信号的第二延迟电路， 与输出缓冲区延迟。

    Input pin control
    29.
    发明授权
    Input pin control 有权
    输入引脚控制

    公开(公告)号：US09417640B2

    公开(公告)日：2016-08-16

    申请号：US14274237

    申请日：2014-05-09

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang ,  Chao-Hsin Lin

    IPC: H03K17/22 ,  G05F1/46

    CPC classification number: G05F1/46 ,  G05F1/468 ,  H03K17/22

    Abstract: An integrated circuit device includes a pad adapted to receive a signal from an external driver. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may correspond to a logic low level or a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the voltage level in response to an event that causes the initialization.

    Abstract translation: 集成电路器件包括适于从外部驱动器接收信号的焊盘。 状态寄存器被编程为响应于该焊盘的状态而指示在集成电路器件的电路初始化期间为焊盘设置的电压电平的状态。 电压电平可以对应于逻辑低电平或逻辑高电平。 电压保持电路耦合到焊盘和状态寄存器，并且被配置为响应于引起初始化的事件而迫使焊盘达到电压电平。

Patent Agency Ranking