公开(公告)号：US11990202B2

公开(公告)日：2024-05-21

申请号：US18047661

申请日：2022-10-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： You-Liang Chou ,  Wen-Jer Tsai

IPC: G11C29/52 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H10B43/35

CPC classification number: G11C29/52 ,  G11C11/5671 ,  G11C16/08 ,  G11C16/10 ,  G11C16/0483 ,  H10B43/35

Abstract: A data recovery method is applied to a memory device which has a target memory cell, a target word line and an adjacent word line adjacent to the target word line. The target word line is connected to a gate of the target memory cell. The adjacent word line is connected to a gate of an adjacent memory cell, and the adjacent memory cell is adjacent to the target memory cell. In the data recovery method, a first program voltage is applied to the target memory cell through the target word line, and a second program voltage is concurrently applied to the adjacent memory cell through the adjacent word line.

公开(公告)号：US11361824B1

公开(公告)日：2022-06-14

申请号：US17164976

申请日：2021-02-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Cheng-Hsien Cheng ,  Chun-Chang Lu ,  Wen-Jer Tsai

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

Abstract: Provided are a memory device and an operation method thereof. The memory device includes a plurality of word lines. The operation method comprising: performing a pre-fill operation on the word lines, in a first loop, applying a selected word line voltage on a first selected word line group and applying an unselected word line voltage on a first unselected word line group, and in a second loop, applying the selected word line voltage on a second selected word line group and applying the unselected word line voltage on a second unselected word line group, the first selected word line group being different from the second selected word line group, and the first unselected word line group being different from the second unselected word line group; performing an erase operation on the word lines; and performing a programming operation on the word lines.

公开(公告)号：US11289502B2

公开(公告)日：2022-03-29

申请号：US16727009

申请日：2019-12-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Liang Lin ,  Wen-Jer Tsai

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/788 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H01L21/3205 ,  H01L21/3213

Abstract: A memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer; a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

公开(公告)号：US20190080750A1

公开(公告)日：2019-03-14

申请号：US15698812

申请日：2017-09-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Ta-Wei Lin ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Wen-Jer Tsai

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.

公开(公告)号：US20160218111A1

公开(公告)日：2016-07-28

申请号：US14604134

申请日：2015-01-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Wen-Jer Tsai

IPC: H01L27/115 ,  G11C16/10 ,  H01L21/324 ,  H01L23/528 ,  H01L21/28 ,  H01L21/265 ,  G11C16/04 ,  G11C16/26

CPC classification number: H01L21/324 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/40117 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device is provided. The memory device includes a substrate, a plurality of semiconductor strip structures, a first doped region, a plurality of second doped regions, a plurality of first contacts, and a plurality of second contacts. Each of the semiconductor strip structures extends along a first direction. The first doped region includes a plurality of first portions and a second portion. Each of the first portions is located on a lower part of the corresponding semiconductor strip structure. The second portion is located on a surface of the substrate, and the first portions are connected to the second portion. Each of the second doped regions is located on an upper part of the corresponding semiconductor strip structure. Each of the first contacts is electrically connected to the second portion of the first doped region. Each of the second contacts is electrically connected to the corresponding second doped region.

Abstract translation: 提供存储器件。 存储器件包括衬底，多个半导体条状结构，第一掺杂区，多个第二掺杂区，多个第一触点和多个第二触点。 每个半导体条结构沿着第一方向延伸。 第一掺杂区域包括多个第一部分和第二部分。 每个第一部分位于相应半导体条结构的下部。 第二部分位于基板的表面上，第一部分连接到第二部分。 每个第二掺杂区域位于相应半导体条结构的上部。 每个第一触点电连接到第一掺杂区域的第二部分。 每个第二触点电连接到相应的第二掺杂区域。

公开(公告)号：US09373629B1

公开(公告)日：2016-06-21

申请号：US14604116

申请日：2015-01-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Guei Yan ,  Chih-Chieh Cheng ,  Wen-Jer Tsai

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L27/115 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/28282 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/11565 ,  H01L27/1157

Abstract: A memory device is provided. The memory device includes a plurality of stack structures, a plurality of first stepped contacts, and a plurality of second stepped contacts. Each of the stack structures extends in a first direction, and includes a first semiconductor layer and a second semiconductor layer. The second semiconductor layer is disposed above the first semiconductor layer. Each of the first stepped contacts extends in a second direction, and a bottom surface thereof is electrically connected to the first semiconductor layers of an i+1th stack structure and an i+2th stack structure, wherein i is an odd number. Each of the second stepped contacts extends in the second direction, and a bottom surface thereof is electrically connected to the second semiconductor layers of an nth stack structure and the i+1th stack structure. The first direction is different from the second direction.

Abstract translation: 提供存储器件。 存储器件包括多个堆叠结构，多个第一阶梯式触点和多个第二阶梯触点。 每个堆叠结构在第一方向上延伸，并且包括第一半导体层和第二半导体层。 第二半导体层设置在第一半导体层的上方。 每个第一阶梯式接触件在第二方向上延伸，并且其底表面电连接到第i + 1个堆叠结构和第i + 2个堆叠结构的第一半导体层，其中i是奇数。 每个第二台阶接触件沿第二方向延伸，并且其底表面电连接到第n堆叠结构的第二半导体层和第i + 1个堆叠结构。 第一个方向与第二个方向不同。

公开(公告)号：US09269583B1

公开(公告)日：2016-02-23

申请号：US14530082

申请日：2014-10-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Guei Yan ,  Chih-Chieh Cheng ,  Wen-Jer Tsai

IPC: H01L21/8244 ,  H01L21/266 ,  H01L27/115 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L21/266 ,  H01L21/2253 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582

Abstract: Provided is a method for fabricating a memory device, including the following steps. A plurality of semiconductor fin structures is formed on a substrate. Each semiconductor fin structure includes a first doped region and a body region on which the first doped region is disposed, and a trench is disposed between adjacent two semiconductor fin structures. A second doped region is formed in the substrate under the body regions of the semiconductor fin structures and the trenches. A plurality of first contacts are formed on the substrate. A plurality of second contacts are formed on the substrate. Each second contact is electrically connected with the corresponding first doped region.

Abstract translation: 提供一种用于制造存储器件的方法，包括以下步骤。 在基板上形成多个半导体翅片结构。 每个半导体鳍片结构包括第一掺杂区域和其上设置有第一掺杂区域的主体区域，并且在相邻的两个半导体鳍片结构之间设置沟槽。 第二掺杂区形成在半导体鳍结构体和沟槽的主体区域下方的衬底中。 在基板上形成多个第一触点。 在基板上形成多个第二触点。 每个第二接触件与相应的第一掺杂区域电连接。

公开(公告)号：US09209198B2

公开(公告)日：2015-12-08

申请号：US14275559

申请日：2014-05-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Wen-Jer Tsai

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: Provided is a memory cell including a substrate, two doped regions of a first conductivity type, one doped region of a second conductivity type, two stacked structures, and a first isolation structure. The doped regions of the first conductivity type are respectively disposed in the substrate. The doped region of the second conductivity type is disposed in the substrate between the two doped regions of the first conductivity type. The stacked structures are disposed on the substrate and respectively cover the corresponding doped regions of the first conductivity type and a portion of the doped region of the second conductivity type. Each of the stacked structures includes one charge storage layer. The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type.

Abstract translation: 提供了一种存储单元，其包括基板，第一导电类型的两个掺杂区域，第二导电类型的一个掺杂区域，两个堆叠结构和第一隔离结构。 第一导电类型的掺杂区域分别设置在基板中。 第二导电类型的掺杂区域设置在第一导电类型的两个掺杂区域之间的衬底中。 层叠结构设置在基板上并分别覆盖第一导电类型的对应掺杂区域和第二导电类型的掺杂区域的一部分。 每个堆叠结构包括一个电荷存储层。 第一隔离结构完全覆盖并与第一导电类型的每个掺杂区的底表面和第二导电类型的掺杂区的底表面接触。

公开(公告)号：US09048263B2

公开(公告)日：2015-06-02

申请号：US14314830

申请日：2014-06-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Cheng-Hsien Cheng ,  Wen-Jer Tsai

IPC: H01L21/8247 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

Abstract: A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers.

Abstract translation: 提供了一种非易失性存储器及其制造方法。 在该方法中，在基板上形成具有突出部的第一氧化物层。 在突起的两侧在衬底中形成一对掺杂区域。 在突起的侧壁上形成一对电荷存储间隔物。 在第一氧化物层和一对电荷存储间隔物上形成第二氧化物层。 导电层形成在第二氧化物层上，其中导电层完全位于一对电荷存储间隔物的顶部上。

公开(公告)号：US20140209992A1

公开(公告)日：2014-07-31

申请号：US13750606

申请日：2013-01-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Wen-Jer Tsai

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11563 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A fabricating method for fabricating a non-volatile memory structure including the following steps is provided. A first conductive type doped layer is formed in a substrate. A plurality of stacked structures is formed on the substrate, and each of the stacked structures includes a charge storage structure. A first dielectric layer is formed on the substrate between the adjacent stacked structures. A second conductive type doped region is formed in the substrate between the adjacent charge storage structures. The second conductive type doped region has an overlap region with each of the charge storage structures. In addition, the second conductive type doped region divides the first conductive type doped layer into a plurality of first conductive type doped regions that are separated from each other. A conductive layer is formed on the first dielectric layer.

Abstract translation: 提供一种用于制造包括以下步骤的非易失性存储器结构的制造方法。 在衬底中形成第一导电型掺杂层。 在基板上形成多个堆叠结构，并且每个堆叠结构都包括电荷存储结构。 在相邻的层叠结构之间的基板上形成第一电介质层。 在相邻的电荷存储结构之间的衬底中形成第二导电型掺杂区。 第二导电型掺杂区域与每个电荷存储结构具有重叠区域。 此外，第二导电型掺杂区域将第一导电类型掺杂层划分成彼此分离的多个第一导电型掺杂区域。 在第一电介质层上形成导电层。