专利检索 ap:("Makarem A. Hussein" OR "Peter Moon" OR "Jim Powers" OR "Kevin P. O'Brien") AND inv:"Kevin P. O'Brien" 第 3 页

21.

发明授权
Vertical meander inductor for small core voltage regulators 有权
标题翻译：用于小型电压调节器的垂直弯曲电感器

公开(公告)号：US08803283B2

公开(公告)日：2014-08-12

申请号：US13629168

申请日：2012-09-27

申请人： Christopher J. Jezewski , Kevin P. O'Brien

发明人： Christopher J. Jezewski , Kevin P. O'Brien

IPC分类号： H01L27/02 , H01L21/20 , H01L49/02

CPC分类号： H01L28/10 , H01L21/4814 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00

摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.

摘要翻译： 描述了用于小型电压调节器的垂直偏转电感器和用于制造小型电压调节器的垂直偏转电感器的方法。例如，半导体管芯包括衬底。集成电路设置在基板的有源表面上。电感器耦合到集成电路。电感器设置成与设置在基板的基本上平坦的表面上的绝缘层共形。绝缘层具有起伏的形貌。

22.

发明授权
Nanotube and metal composite interconnects 有权
标题翻译：纳米管和金属复合互连

公开(公告)号：US07843070B2

公开(公告)日：2010-11-30

申请号：US12034635

申请日：2008-02-20

申请人： Kevin P. O'Brien

发明人： Kevin P. O'Brien

IPC分类号： H01L29/66

CPC分类号： H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/81 , H01L2924/00

摘要： Nanotube and metal composite interconnects are generally described. In one example, an apparatus includes an interlayer dielectric (ILD) and one or more interconnect structures coupled to the ILD, the one or more interconnect structures including a composite of metal and one or more nanotubes.

摘要翻译： 纳米管和金属复合互连通常被描述。在一个示例中，装置包括层间电介质（ILD）和耦合到ILD的一个或多个互连结构，所述一个或多个互连结构包括金属和一个或多个纳米管的复合物。

23.

发明授权
Photoactive adhesion promoter in a slam 失效
标题翻译：光敏助粘剂

公开(公告)号：US07723008B2

公开(公告)日：2010-05-25

申请号：US11087181

申请日：2005-03-22

申请人： Robert P. Meagley , Heidi B. Cao , Kevin P. O'Brien

发明人： Robert P. Meagley , Heidi B. Cao , Kevin P. O'Brien

IPC分类号： G03C1/00

CPC分类号： G03F7/091 , G03F7/0045

摘要： A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution, and limited depth of focus problems associated with the removal of a photoresist layer. More particularly, embodiments of the invention use a photoacid generator (PAG) material in conjunction with a sacrificial light absorbing material (SLAM) to help reduce these and other undesired effects associated with the removal of photoresist in a semiconductor manufacturing process. Furthermore, embodiments of the invention allow a PAG to be applied in a semiconductor manufacturing process in an efficient manner, requiring fewer processing operations than typical prior art techniques.

摘要翻译： 有助于减少半导体工艺效应的半导体工艺技术，例如不期望的线边缘粗糙度，光刻分辨率不足以及与去除光致抗蚀剂层相关的有限的焦深问题。更具体地，本发明的实施例使用光致酸产生剂（PAG）材料结合牺牲光吸收材料（SLAM）来帮助减少在半导体制造过程中与去除光致抗蚀剂有关的这些和其它不期望的影响。此外，本发明的实施例允许PAG以有效的方式应用于半导体制造过程中，与典型的现有技术相比需要较少的处理操作。

24.

发明授权
Formation of air gaps in an interconnect structure using a thin permeable hard mask and resulting structures 有权
标题翻译：使用薄的可渗透硬掩模和所得结构在互连结构中形成气隙

公开(公告)号：US07294568B2

公开(公告)日：2007-11-13

申请号：US10922617

申请日：2004-08-20

申请人： Michael D. Goodner , Kevin P. O'Brien , Grant M. Kloster

发明人： Michael D. Goodner , Kevin P. O'Brien , Grant M. Kloster

IPC分类号： H01L21/4763 , H01L21/764

CPC分类号： H01L21/76807 , H01L21/7682

摘要： A method of forming air gaps in the interconnect structure of an integrated circuit device. The air gaps may be formed by depositing sacrificial layer over a dielectric layer and then depositing a permeable hard mask over the sacrificial layer. The sacrificial layer is subsequently removed to form air gaps. The permeable hard mask may have a thickness of less than approximately 250 nm, and internal stresses within the permeable hard mask may be controlled to prevent deformation of this layer. Other embodiments are described and claimed.

摘要翻译： 一种在集成电路器件的互连结构中形成气隙的方法。气隙可以通过在介电层上沉积牺牲层然后在牺牲层上沉积可渗透的硬掩模来形成。随后去除牺牲层以形成气隙。可渗透的硬掩模可以具有小于约250nm的厚度，并且可以控制可渗透硬掩模内的内应力以防止该层的变形。描述和要求保护其他实施例。

25.

发明授权
Semiconductor device formed with an air gap using etch back of inter layer dielectric (ILD) 失效
标题翻译：使用层间电介质（ILD）的后蚀刻形成有气隙的半导体器件

公开(公告)号：US07126223B2

公开(公告)日：2006-10-24

申请号：US10261426

申请日：2002-09-30

申请人： James Powers , Kevin P. O'Brien

发明人： James Powers , Kevin P. O'Brien

IPC分类号： H01L23/52

CPC分类号： H01L23/5226 , H01L21/7682 , H01L23/5222 , H01L2924/0002 , H01L2924/00

摘要： A method is disclosed of forming an air gap using etch back of an inter layer dielectric (ILD) with self-alignment to metal pattern. The method entails forming a first metallization layer deposited on a first dielectric, forming a second metallization layer deposited on a second dielectric, wherein the second metallization layer is spaced apart from the first metallization layer, forming a sacrificial ILD between the first and second metallization layers, forming a diffusion layer over the first and second metallization layers and over the sacrificial ILD, and removing the sacrificial ILD to form an air gap between the first and second metallization layers. This method is particular applicable for dual copper damascene processes.

摘要翻译： 公开了一种使用具有自对准金属图案的层间电介质（ILD）的回蚀形成气隙的方法。该方法需要形成沉积在第一电介质上的第一金属化层，形成沉积在第二电介质上的第二金属化层，其中第二金属化层与第一金属化层间隔开，在第一和第二金属化层之间形成牺牲ILD 在所述第一和第二金属化层上并在所述牺牲ILD上形成扩散层，以及去除所述牺牲ILD以在所述第一和第二金属化层之间形成气隙。该方法特别适用于双铜镶嵌工艺。

26.

发明授权
Method of fabricating a bismaleimide (BMI) ASA sacrifical material for an integrated circuit air gap dielectric 失效
标题翻译：制造用于集成电路气隙电介质的双马来酰亚胺（BMI）ASA牺牲材料的方法

公开(公告)号：US06872654B2

公开(公告)日：2005-03-29

申请号：US10330619

申请日：2002-12-26

申请人： Tian-An Chen , Kevin P. O'Brien

发明人： Tian-An Chen , Kevin P. O'Brien

IPC分类号： H01L21/312 , H01L21/768 , H01L21/4763

CPC分类号： H01L21/7682 , H01L21/02118 , H01L21/02203 , H01L21/02282 , H01L21/02348 , H01L21/312

摘要： A method for implementing a bismaleimide (BMI) polymer as a sacrificial material for an integrated circuit air gap dielectric. The method of one embodiment comprises forming a first and second metal interconnect lines on a substrate, wherein at least a portion of the first and second metal interconnect lines extend parallel to one another and wherein a trough is located between the parallel portion of said first and second metal interconnect lines. A layer of bismaleimide is spin coated over the substrate. The layer of bismaleimide is polished with a chemical mechanical polish, wherein the trough remains filled with the bismaleimide. A diffusion layer is formed over the substrate. The substrate is heated to activate a pyrolysis of the bismaleimide. An air gap is formed in the trough in the space vacated by the bismaleimide.

摘要翻译： 一种用于实现用于集成电路气隙电介质的双马来酰亚胺（BMI）聚合物作为牺牲材料的方法。一个实施例的方法包括在衬底上形成第一和第二金属互连线，其中第一和第二金属互连线的至少一部分彼此平行延伸，并且其中槽位于所述第一和第二金属互连线的平行部分之间，第二金属互连线。将一层双马来酰亚胺旋涂在基材上。用化学机械抛光剂抛光双马来酰亚胺层，其中槽保持充满双马来酰亚胺。在衬底上形成扩散层。加热底物以活化双马来酰亚胺的热解。在由双马来酰亚胺空出的空间中的槽中形成气隙。

27.

发明申请
MEMORY CELLS WITH ENHANCED TUNNELING MAGNETORESISTANCE RATIO, MEMORY DEVICES AND SYSTEMS INCLUDING THE SAME 审中-公开

公开(公告)号：US20180350418A1

公开(公告)日：2018-12-06

申请号：US15779029

申请日：2015-12-24

申请人： Brian S. Doyle , Elijah V. Karpov , Kaan Oguz , Kevin P. O'Brien , Charles C. Kuo , Mark L. Doczy , Uday Shah , Yih Wang

发明人： Brian S. Doyle , Elijah V. Karpov , Kaan Oguz , Kevin P. O'Brien , Charles C. Kuo , Mark L. Doczy , Uday Shah , Yih Wang

IPC分类号： G11C11/16 , G11C11/56 , H01L43/08 , H01L27/22

CPC分类号： G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5607 , G11C2211/5615 , H01L27/228 , H01L43/08

摘要： Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.

28.

发明授权
Vertical meander inductor for small core voltage regulators 有权
标题翻译：用于小型电压调节器的垂直弯曲电感器

公开(公告)号：US09129844B2

公开(公告)日：2015-09-08

申请号：US14319429

申请日：2014-06-30

申请人： Christopher J. Jezewski , Kevin P. O'Brien

发明人： Christopher J. Jezewski , Kevin P. O'Brien

IPC分类号： H01L49/02 , H01L21/48 , H01L23/64 , H01L23/522

CPC分类号： H01L28/10 , H01L21/4814 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/00

摘要： Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.

摘要翻译： 描述了用于小型电压调节器的垂直偏转电感器和用于制造小型电压调节器的垂直偏转电感器的方法。例如，半导体管芯包括衬底。集成电路设置在基板的有源表面上。电感器耦合到集成电路。电感器设置成与设置在基板的基本上平坦的表面上的绝缘层共形。绝缘层具有起伏的形貌。

29.

发明申请
MAGNETIC CORE INDUCTOR (MCI) STRUCTURES FOR INTEGRATED VOLTAGE REGULATORS 有权
标题翻译：集成电压调节器的磁芯电感（MCI）结构

公开(公告)号：US20140264732A1

公开(公告)日：2014-09-18

申请号：US13801623

申请日：2013-03-13

申请人： Adel A. Elsherbini , Kevin P. O'Brien , Henning Braunisch , Krishna Bharath

发明人： Adel A. Elsherbini , Kevin P. O'Brien , Henning Braunisch , Krishna Bharath

IPC分类号： H01L27/06

CPC分类号： H01L27/06 , H01F17/0006 , H01F2017/0066 , H01L23/64 , H01L25/16 , H01L27/016 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00

摘要： Semiconductor packages including magnetic core inductor (MCI) structures for integrated voltage regulators are described. In an example, a semiconductor package includes a package substrate and a semiconductor die coupled to a first surface of the package substrate. The semiconductor die has a first plurality of metal-insulator-metal (MIM) capacitor layers thereon. The semiconductor package also includes a magnetic core inductor (MCI) die coupled to a second surface of the package substrate. The MCI die includes one or more slotted inductors and has a second plurality of MIM capacitor layers thereon.

摘要翻译： 描述了包括集成稳压器的磁芯电感（MCI）结构的半导体封装。在一个示例中，半导体封装包括封装衬底和耦合到封装衬底的第一表面的半导体管芯。半导体管芯在其上具有第一多个金属 - 绝缘体 - 金属（MIM）电容器层。半导体封装还包括耦合到封装衬底的第二表面的磁芯电感器（MCI）裸芯片。 MCI管芯包括一个或多个开槽电感器，并且其上具有第二多个MIM电容器层。