公开(公告)号：USRE41980E1

公开(公告)日：2010-12-07

申请号：US11984551

申请日：2007-11-19

申请人： Toshiki Yabu ,  Mizuki Segawa

发明人： Toshiki Yabu ,  Mizuki Segawa

IPC分类号： H01L29/41

CPC分类号： H01L24/05 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/30105 ,  Y10S257/915 ,  H01L2924/00014

摘要： A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented. In this manner, the invention provides a semiconductor device which has a small parasitic capacitance in an area with a small pitch between the metal wires and is free from a coverage defect as well as the moisture absorption through the opening for the bonding pad, and a method of manufacturing the semiconductor device.

摘要翻译： 多个金属线形成在下面的层间绝缘膜上。 金属线中的区域填充有介电常数小的氧化硅膜的掩埋绝缘膜（即，第一介电膜），因此可以降低金属线的寄生电容。 在掩埋绝缘膜上形成具有高耐吸湿性（即第二介电膜）的氮化硅膜的钝化膜，因此可以避免覆盖缺陷。 接合焊盘被埋在形成在包括掩埋绝缘膜和钝化膜的表面保护膜的一部分中的开口中，以便不在开口内露出掩埋绝缘膜。 因此，可以防止通过开口的吸湿。 以这种方式，本发明提供了一种半导体器件，其在金属线之间具有小间距的区域中具有小的寄生电容，并且没有覆盖缺陷以及通过用于焊盘的开口的吸湿性，以及 制造半导体器件的方法。

公开(公告)号：US06524904B1

公开(公告)日：2003-02-25

申请号：US09551542

申请日：2000-04-18

申请人： Mizuki Segawa ,  Masatoshi Arai ,  Toshiki Yabu ,  Shunsuke Kugo

发明人： Mizuki Segawa ,  Masatoshi Arai ,  Toshiki Yabu ,  Shunsuke Kugo

IPC分类号： H01L218238

CPC分类号： H01L21/823842

摘要： After P+ ions are implanted into a polysilicon film in an nMOSFET region, a heat treatment is performed to diffuse phosphorus down to the lower part of the polysilicon film. The diffusion reduces the concentration of phosphorus in an upper end portion of the polysilicon film and inhibits the upper end edges of a gate electrode from being increased in size during patterning. Then, B+ ions are implanted into the polysilicon film in a pMOSFET region and the polysilicon film is etched into a gate configuration. Since a heat treatment for simultaneously diffusing phosphorus and boron in the polysilicon film is not performed, the entrance of boron from the gate electrode into a semiconductor substrate is inhibited, while the occurrence of side etching during the formation of an n-type polysilicon gate is suppressed.

摘要翻译： 将P +离子注入nMOSFET区域中的多晶硅膜之后，进行热处理以将磷扩散到多晶硅膜的下部。 扩散减少了多晶硅膜的上端部分中的磷的浓度，并且在图案化期间抑制栅电极的上端边缘的尺寸增大。 然后，在pMOSFET区域中将B +离子注入到多晶硅膜中，并且将多晶硅膜蚀刻成栅极配置。 由于不进行同时扩散多晶硅膜中的磷和硼的热处理，可以抑制从栅极引入到半导体衬底中的硼，同时在形成n型多晶硅栅极时发生侧蚀刻是 被压制

公开(公告)号：US5989992A

公开(公告)日：1999-11-23

申请号：US925442

申请日：1997-09-08

申请人： Toshiki Yabu ,  Mizuki Segawa

发明人： Toshiki Yabu ,  Mizuki Segawa

IPC分类号： H01L21/60 ,  H01L21/316 ,  H01L21/318 ,  H01L21/3205 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L23/3171 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/30105 ,  Y10S257/915

摘要： A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented. In this manner, the invention provides a semiconductor device which has a small parasitic capacitance in an area with a small pitch between the metal wires and is free from a coverage defect as well as the moisture absorption through the opening for the bonding pad, and a method of manufacturing the semiconductor device.

摘要翻译： 多个金属线形成在下面的层间绝缘膜上。 金属线中的区域填充有介电常数小的氧化硅膜的掩埋绝缘膜（即，第一介电膜），因此可以降低金属线的寄生电容。 在掩埋绝缘膜上形成具有高耐吸湿性（即第二介电膜）的氮化硅膜的钝化膜，因此可以避免覆盖缺陷。 接合焊盘被埋在形成在包括掩埋绝缘膜和钝化膜的表面保护膜的一部分中的开口中，以便不在开口内露出掩埋绝缘膜。 因此，可以防止通过开口的吸湿。 以这种方式，本发明提供了一种半导体器件，其在金属线之间具有小间距的区域中具有小的寄生电容，并且没有覆盖缺陷以及通过用于焊盘的开口的吸湿性，以及 制造半导体器件的方法。

公开(公告)号：US5399890A

公开(公告)日：1995-03-21

申请号：US257955

申请日：1994-06-10

申请人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

发明人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.

摘要翻译： 本发明的半导体存储器包括具有多个晶体管的半导体衬底，与多个晶体管的一部分连接的多个叠层电容器，与多个晶体管的其它部分连接的多个第一级互连层，以及多个晶体管的多个 位于层叠电容器和第一级互连层之上的第二级互连层。 多个叠层电容器中的每一个包括第一电极层，形成在第一电极层顶部的电容绝缘膜，以及形成在电容绝缘膜顶部的第二电极层。 第二电极层连接到多个第二级互连层之一的一部分。 多个第一级互连层的至少一部分连接到多个第二级互连层的其它部分。 多个第一级互连层中的每一个与第一电极层和第二电极层中的至少一个共享相同的层。

公开(公告)号：US5217914A

公开(公告)日：1993-06-08

申请号：US683603

申请日：1991-04-10

申请人： Susumu Matsumoto ,  Toshiki Yabu ,  Yoshiro Nakata ,  Naoto Matsuo ,  Shozo Okada ,  Hiroyuki Sakai

发明人： Susumu Matsumoto ,  Toshiki Yabu ,  Yoshiro Nakata ,  Naoto Matsuo ,  Shozo Okada ,  Hiroyuki Sakai

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/91

摘要： Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.

摘要翻译： 公开了具有层叠电容器单元的半导体积分电路。 每个单元包括用于存储电荷的电荷存储电极，以及集成在其上的电容器绝缘膜和相对的平板电极。 电荷存储电极基本上由至少双框状部分或至少一个柱状部分中的底部和部分组成，以及围绕从底面向上升起的柱状部分的至少一个框状部分。 电容器沉积膜由沉积在电荷存储电极的所有底面和所有表面上的介电材料膜构成，并与相对的板电极配合构建电容器。 所述制造叠层电容器电池的方法可以通过重复氧化膜和导电膜的沉积以及各向异性蚀刻来形成自对准电容器。

公开(公告)号：US06346736B1

公开(公告)日：2002-02-12

申请号：US09469498

申请日：1999-12-22

申请人： Takaaki Ukeda ,  Chiaki Kudo ,  Toshiki Yabu

发明人： Takaaki Ukeda ,  Chiaki Kudo ,  Toshiki Yabu

IPC分类号： H01L3300

CPC分类号： H01L23/5222 ,  H01L21/76232 ,  H01L2924/0002 ,  H01L2924/00

摘要： The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the interlayer insulating film. What results is a semiconductor device having lower total wiring-to-substrate capacitance and a higher operating speed.

摘要翻译： P型半导体衬底的顶表面被划分为有源区域，以形成元件和围绕有源区域的隔离区域。 隔离区域由沟槽部分和虚拟半导体部分组成。 在基板上沉积层间绝缘膜，然后在其上形成线。 在每个半导体部分中，与将离子注入到元件中同时形成杂质扩散层，使得在杂质扩散层和硅衬底之间形成PN结。 通过将杂质扩散层中的电容串联添加到层间绝缘膜中的电容而获得包含半导体部分的区域中的布线对基板电容的电容分量，该电容小于仅在中间层 绝缘膜。 具有较低的总布线对基板电容和更高的运行速度的半导体器件的结果是什么。

公开(公告)号：US6069055A

公开(公告)日：2000-05-30

申请号：US886859

申请日：1997-07-01

申请人： Takaaki Ukeda ,  Toshiki Yabu ,  Takashi Uehara ,  Mizuki Segawa ,  Masatoshi Arai ,  Masaru Moriwaki

发明人： Takaaki Ukeda ,  Toshiki Yabu ,  Takashi Uehara ,  Mizuki Segawa ,  Masatoshi Arai ,  Masaru Moriwaki

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/76232

摘要： The fabricating method for semiconductor devices in which the trench technique is employed to perform isolation between devices, and which comprises the steps of sequentially depositing a first film 2, 3 and a second film 4 on top of a silicon substrate 1, forming an element isolation trench 5 in the silicon substrate 1 with masking of the first film 2, 3 and second film 4 which have undergone patterning, and growing a silicon oxide film 6 that is generated by reaction of ozone and tetra-ethyl-ortho-silicate inside the element isolation trench where silicon is exposed.

摘要翻译： 采用沟槽技术来进行器件之间的隔离的半导体器件的制造方法，其包括以下步骤：在硅衬底1的顶部依次沉积第一膜2,3和第二膜4，形成元件隔离 硅衬底1中的沟槽5，其具有被图案化的第一膜2,3和第二膜4的掩蔽，并且通过在元件内的臭氧和四乙基原硅酸盐的反应产生氧化硅膜6 硅暴露的隔离沟槽。

公开(公告)号：US6034416A

公开(公告)日：2000-03-07

申请号：US61071

申请日：1998-04-16

申请人： Takashi Uehara ,  Toshiki Yabu ,  Mizuki Segawa ,  Takaaki Ukeda ,  Masatoshi Arai ,  Masaru Moriwaki

发明人： Takashi Uehara ,  Toshiki Yabu ,  Mizuki Segawa ,  Takaaki Ukeda ,  Masatoshi Arai ,  Masaru Moriwaki

IPC分类号： H01L21/8247 ,  H01L29/72

CPC分类号： H01L27/11526 ,  H01L27/11539

摘要： The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions. In a flash-integrated logic LSI incorporating a nonvolatile memory cell, a density can be increased in the memory cell region and the peripheral circuit region and the costs can be reduced.

摘要翻译： 外围电路区域中的衬底的顶表面处于比存储单元区域中的衬底顶表面高的位置，并且基本上等于浮栅电极的顶表面。 通过栅极绝缘膜在浮栅上形成控制栅电极，通过栅极绝缘膜在外围电路区域的基板上形成栅电极。 如果控制栅电极由多层膜形成，用于沟槽隔离的掩埋绝缘膜的顶表面可以处于等于浮栅电极的顶表面或底层膜的顶表面的水平。 可以减小存储单元区域中的控制栅电极与外围电路区域中的栅电极之间的电平差，从而可以在这些区域中形成精细图案。 在包含非易失性存储单元的闪存集成逻辑LSI中，可以在存储单元区域和外围电路区域中增加密度，并且可以降低成本。

公开(公告)号：US5972783A

公开(公告)日：1999-10-26

申请号：US796710

申请日：1997-02-06

申请人： Masatoshi Arai ,  Mizuki Segawa ,  Toshiki Yabu

发明人： Masatoshi Arai ,  Mizuki Segawa ,  Toshiki Yabu

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L29/732 ,  H01L29/78 ,  H01L21/223

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/28176 ,  H01L29/512 ,  H01L29/66272 ,  H01L29/6659 ,  H01L29/7322 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/518

摘要： An element isolator is formed in a silicon substrate. A gate oxide film and a gate electrode are formed overlying the silicon substrate. Subsequently, a four-step large-tilted-angle ion implant is performed in which ions of nitrogen are implanted at an angle of tilt of 25 degrees, to form an oxynitride layer at each edge of the gate oxide film and to form a nitrogen diffusion layer in the silicon substrate. This is followed by formation of a lightly-doped source/drain region by means of impurity doping. A sidewall is formed on each side surface of the gate electrode, which is followed by formation of a heavily-doped source/drain region by impurity doping. The present invention provides an improved semiconductor device having high-performance, highly-reliable MOS field effect transistors and a method for fabricating the same.

摘要翻译： 元件隔离器形成在硅衬底中。 在硅衬底上形成栅极氧化膜和栅电极。 随后，进行四步大倾角离子注入，其中以25度的倾斜角度注入氮离子，以在栅极氧化膜的每个边缘处形成氧氮化物层并形成氮扩散 在硅衬底中。 随后通过杂质掺杂形成轻掺杂的源/漏区。 在栅极的每个侧表面上形成侧壁，随后通过杂质掺杂形成重掺杂的源极/漏极区。 本发明提供一种具有高性能，高可靠性MOS场效应晶体管的改进的半导体器件及其制造方法。

公开(公告)号：US5879983A

公开(公告)日：1999-03-09

申请号：US716571

申请日：1996-09-18

申请人： Mizuki Segawa ,  Toshiki Yabu ,  Takashi Uehara ,  Takashi Nakabayashi ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada

发明人： Mizuki Segawa ,  Toshiki Yabu ,  Takashi Uehara ,  Takashi Nakabayashi ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada

IPC分类号： H01L29/43 ,  H01L21/02 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8242

CPC分类号： H01L27/11526 ,  H01L21/82345 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11543 ,  H01L28/40 ,  Y10S438/957

摘要： A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled. In the semiconductor device in which a transistor, a capacitive element, a resistive film and the like are provided, the occupied area can be reduced and the manufacturing cost can be cut down.