公开(公告)号：US20180047660A1

公开(公告)日：2018-02-15

申请号：US15233906

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  David Francis BERDY ,  Daeik Daniel KIM ,  Jonghae KIM

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49805 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L24/02 ,  H05K1/0218 ,  H05K3/3436 ,  H05K2201/10719

Abstract: A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.

公开(公告)号：US20170372975A1

公开(公告)日：2017-12-28

申请号：US15191062

申请日：2016-06-23

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  David Francis BERDY ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  Jonghae KIM

IPC: H01L21/66 ,  H01L23/544 ,  H01L23/66

CPC classification number: H01L22/32 ,  H01L23/544 ,  H01L27/13 ,  H01L2223/5446 ,  H01L2223/54493 ,  H03H7/00 ,  H03H7/1766 ,  H03H7/1791 ,  H03H7/463 ,  H03H2001/0078 ,  H04B1/0057

Abstract: A radio frequency (RF) integrated circuit may include a die having passive components including at least one pair of capacitors covered by a first dielectric layer supported by the die. The RF integrated circuit may also include an inline pad structure coupled to the at least one pair of capacitors proximate an edge of the die. The inline pad structure may include a first portion and a second portion extending into a dicing street toward the edge of the die and covered by at least a second dielectric layer.

公开(公告)号：US20170338788A1

公开(公告)日：2017-11-23

申请号：US15161138

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Jonghae KIM ,  Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA

IPC: H03H7/01 ,  H05K3/18 ,  H05K3/00 ,  H05K1/11 ,  H03H1/00 ,  H05K1/03 ,  H05K1/02 ,  H05K3/40 ,  H05K1/16

CPC classification number: H03H7/1758 ,  H01F5/003 ,  H01F41/04 ,  H01F41/041 ,  H01P1/203 ,  H01P1/2135 ,  H01P5/12 ,  H03H1/00 ,  H03H7/0115 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/1775 ,  H03H7/463 ,  H03H2001/0078 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/186 ,  H05K3/0026 ,  H05K3/18 ,  H05K3/4038

Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.

公开(公告)号：US20170200550A1

公开(公告)日：2017-07-13

申请号：US14991803

申请日：2016-01-08

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  David Francis BERDY ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Jonghae KIM

IPC: H01F27/28 ,  H04B1/40 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F41/041 ,  H01L23/5222 ,  H01L23/5227 ,  H01L27/0207 ,  H01L28/10 ,  H04B1/40

Abstract: A skewed, co-spiral inductor structure may include a first trace arranged in a first spiral pattern that is supported by a substrate. The skewed, co-spiral inductor structure may also include a second trace arranged in a second spiral pattern, in which the second trace is coupled to the first trace. The first trace may overlap with the second trace in orthogonal overlap areas. In addition, each orthogonal overlap area may have a size defined by a width of the first trace and the width of the second trace. Also, parallel edges of the first trace and the second trace may be arranged to coincide.

公开(公告)号：US20170077093A1

公开(公告)日：2017-03-16

申请号：US15298124

申请日：2016-10-19

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  David Francis BERDY ,  Je-Hsiung Jeffrey LAN ,  Changhan Hobie YUN ,  Jonghae KIM

IPC: H01L27/08 ,  H01L29/93 ,  H01L21/78 ,  H01L29/66

CPC classification number: H01L27/0808 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/78 ,  H01L27/1203 ,  H01L29/66174 ,  H01L29/66181 ,  H01L29/93

Abstract: A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.

Abstract translation: 对称变容二极管结构可以包括第一变容二极管组件。 第一变容二极管分量可以包括作为第二板操作的栅极，作为电介质层工作的栅极氧化物层和作为区域调制电容器的第一板工作的主体。 此外，掺杂区域可围绕第一变容二极管部件的主体。 第一变容二极管组件可以由隔离层在背面支撑。 对称变容二极管结构还可以包括通过背侧导电层电耦合到第一变容二极管部件的背侧的第二变容二极管部件。

公开(公告)号：US20160020013A1

公开(公告)日：2016-01-21

申请号：US14335609

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01F27/28 ,  H01F41/04 ,  H01F27/29

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/29 ,  H01F2017/004 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

公开(公告)号：US20190081607A1

公开(公告)日：2019-03-14

申请号：US15705035

申请日：2017-09-14

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Jonghae KIM ,  Changhan Hobie YUN ,  David Francis BERDY ,  Shiqun GU ,  Chengjie ZUO

IPC: H03H7/01 ,  H01L49/02 ,  H01L23/532 ,  H03H3/00 ,  H01L27/01 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated device that includes a substrate, a first interconnect over the substrate and a second interconnect comprising a first portion and a second portion. The integrated device further comprising a first dielectric layer between the first interconnect and the first portion of the second interconnect such that the first interconnect vertically overlaps with the first dielectric layer and the first portion of the second interconnect. The integrated device also includes a second dielectric layer formed over the substrate. The first interconnect, the first dielectric layer and the first portion of the second interconnect are configured to operate as a capacitor. The first portion and the second portion of the second interconnect are configured to operate as an inductor.

公开(公告)号：US20180167054A1

公开(公告)日：2018-06-14

申请号：US15379392

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Changhan Hobie YUN ,  Shiqun GU ,  Niranjan Sunil MUDAKATTE ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  Jonghae KIM

IPC: H03H9/64 ,  H03H3/08 ,  H03H9/72

CPC classification number: H03H9/64 ,  H03H3/08 ,  H03H9/0523 ,  H03H9/0547 ,  H03H9/0561 ,  H03H9/059 ,  H03H9/72

Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.

公开(公告)号：US20180090475A1

公开(公告)日：2018-03-29

申请号：US15275068

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Jonghae KIM ,  David Francis BERDY ,  Changhan Hobie YUN ,  Niranjan Sunil MUDAKATTE ,  Mario Francisco VELEZ ,  Shiqun GU

IPC: H01L27/01 ,  H01L23/31 ,  H01L23/552 ,  H01L23/528 ,  H01L23/498 ,  H01L21/768 ,  H01L21/56 ,  H01L23/522 ,  H03H7/01 ,  H03H7/46 ,  H04B1/00

CPC classification number: H01L27/01 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49805 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/19011 ,  H01L2924/3025 ,  H03H7/0115 ,  H03H7/468 ,  H04B1/0057 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate supporting the die, a molding compound surrounding the die. The integrated circuit device further includes a backside conductive layer on a surface of the die that is distal from the IPD layer. The integrated circuit device also includes vias coupling the backside conductive layer to a ground plane through the molding compound.

公开(公告)号：US20180077803A1

公开(公告)日：2018-03-15

申请号：US15261838

申请日：2016-09-09

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE ,  Mario Francisco VELEZ ,  Shiqun GU

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K3/30 ,  H05K3/40

CPC classification number: H05K1/185 ,  H01G4/224 ,  H01G4/236 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/52 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4682 ,  H05K3/4688

Abstract: Due to the presence of a glass substrate, it is difficult to fabricate thin conventional passive-on-glass (POG) devices. Also glass dicing has been a throughput bottleneck in fabricating the conventional POG device. To address such disadvantages, devices without the glass substrates are proposed. Support structures may be provided to provide mechanical support. The devices are significantly thinner and allow access to the passive components from both first and second surfaces, which are opposite and exposed surfaces. The proposed POM devices may also be incorporated in a package substrate.