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    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT
    21.
    发明申请
    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT 审中-公开

    公开(公告)号：US20200264782A1

    公开(公告)日：2020-08-20

    申请号：US16805535

    申请日：2020-02-28

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F3/06 ,  G11C7/10 ,  G11C5/04 ,  G06F12/06

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

    Data transmission using delayed timing signals
    22.
    发明授权
    Data transmission using delayed timing signals 有权

    公开(公告)号：US10700671B2

    公开(公告)日：2020-06-30

    申请号：US15824892

    申请日：2017-11-28

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian S. Leibowitz ,  Jared Zerbe

    IPC: H03K5/13 ,  G06F13/16 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22 ,  G06F13/42 ,  G06F13/00 ,  G11C7/04

    Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

    Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
    24.
    发明申请
    Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device 审中-公开

    公开(公告)号：US20190259447A1

    公开(公告)日：2019-08-22

    申请号：US16214986

    申请日：2018-12-10

    Applicant: Rambus Inc.

    Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

    IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4076 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4094 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/065 ,  H01L25/10

    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

    Memory system with threaded transaction support
    27.
    发明授权
    Memory system with threaded transaction support 有权

    公开(公告)号：US11809712B2

    公开(公告)日：2023-11-07

    申请号：US17586575

    申请日：2022-01-27

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G06F12/06

    CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0607 ,  G11C5/04 ,  G11C7/10

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

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