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    Semiconductor device and method for manufacturing the same
    21.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08786046B2

    公开(公告)日：2014-07-22

    申请号：US13910352

    申请日：2013-06-05

    Applicant: Renesas Electronics Corporation

    Inventor： Tomohiro Tamaki ,  Yoshito Nakazawa ,  Satoshi Eguchi

    IPC: H01L29/06

    CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

    Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

    Abstract translation: 解决超结结构的以下问题的半导体装置：由于体细胞区域（有源区域）的相对高的浓度，在周边区域（周边区域或结合区域）中难以实现击穿电压 等于或高于通过常规的连接边缘端子结构或再结构的单元区域。 半导体器件包括通过沟槽填充技术在单元区域中形成的具有超结结构的功率MOSFET。 此外，在细胞区域周围的漂移区域中设置具有与细胞区域的侧面平行的取向的超结结构。

    Vertical power MOSFET
    24.
    发明授权
    Vertical power MOSFET 有权
    垂直功率MOSFET

    公开(公告)号：US09041070B2

    公开(公告)日：2015-05-26

    申请号：US14109208

    申请日：2013-12-17

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Satoshi Eguchi ,  Yoshito Nakazawa ,  Tomohiro Tamaki

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/0619 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811

    Abstract: When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.

    Abstract translation: 当通过嵌入式外延法形成超级结时，通常在沟槽形成蚀刻中进行干蚀刻的锥角调整以形成倾斜的列，以便防止由嵌入的外延层中的浓度波动引起的击穿电压的降低 。 然而，根据本发明人的考察，已经清楚的是，这种方法使得设计越来越难以响应较高的击穿电压。 在本发明中，在构成超结的每个衬底外延柱区域中的中间衬底外延柱区域中的浓度比在衬底外延柱区域内的其它区域的浓度高， 嵌入式外延法。

    Semiconductor device and manufacturing method of the same
    27.
    发明授权
    Semiconductor device and manufacturing method of the same 有权
    半导体器件及其制造方法相同

    公开(公告)号：US08618594B2

    公开(公告)日：2013-12-31

    申请号：US13770213

    申请日：2013-02-19

    Applicant: Renesas Electronics Corporation

    Inventor： Atsushi Shinbori ,  Yoshito Nakazawa

    IPC: H01L29/66

    CPC classification number: H01L27/088 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/7815 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/00

    Abstract: The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate.

    Abstract translation: 本发明提供了一种能够在配备有电流检测电路的沟槽栅型功率MISFET中提高电流检测精度的技术。 非活性单元被设置成围绕感测单元的周边。 也就是说，非活动单元被提供在感测单元和活动单元之间。 所有感测单元，有源电池和非活性单元分别由配备有虚拟栅电极的沟槽栅型功率MISFET形成。 此时，每个沟槽的深度延伸穿过沟道形成区，并形成为n型外延层的深内（与半导体衬底的边界附近）。 此外，p型半导体区域设置在每个沟槽的下部。 形成p型半导体区域以与半导体衬底接触。

    Semiconductor device
    28.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10475882B2

    公开(公告)日：2019-11-12

    申请号：US15971139

    申请日：2018-05-04

    Applicant: Renesas Electronics Corporation

    Inventor： Shigeaki Saito ,  Yoshito Nakazawa ,  Hitoshi Matsuura ,  Yukio Takahashi

    IPC: H01L29/06 ,  H01L29/739 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/04

    Abstract: The reliability of a semiconductor device is improved. A contact trench for coupling a field plate and a field limiting ring situated at the corner part of a semiconductor device is formed of a first straight line part and a second straight line part arranged line symmetrically with respect to the crystal orientation . Respective one ends of the first straight line part and the second straight line part are coupled at the crystal orientation , and the first straight line part and the second straight line part are set to extend in different directions from the crystal orientation and the crystal orientation .

    SEMICONDUCTOR DEVICE
    30.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160133505A1

    公开(公告)日：2016-05-12

    申请号：US14995996

    申请日：2016-01-14

    Applicant: Renesas Electronics Corporation

    Inventor： Satoshi Eguchi ,  Yoshito Nakazawa

    IPC: H01L21/761 ,  H01L21/265

    CPC classification number: H01L21/761 ,  H01L21/0415 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/861

    Abstract: A method for manufacturing a semiconductor device including a cell region and a peripheral region formed outside the cell region, comprising the steps of (a) providing a semiconductor substrate including a first epitaxial layer of a first conductivity type formed over a main surface thereof, (b) doping a lower band gap impurity for making the band gap smaller than the band gap of the first epitaxial layer before doping into the first epitaxial layer in the cell region, and thereby forming a lower band gap region, (c) after the step (b), forming a plurality of first column regions of a second conductivity type which is the opposite conductivity type to the first conductivity type in such a manner as to be separated from one another in the first epitaxial layer extending from the cell region to the peripheral region, and (d) after the step (c), forming a second epitaxial layer.

    Abstract translation: 一种制造半导体器件的方法，该半导体器件包括形成在晶胞区外的单元区域和周边区域，包括以下步骤：（a）提供包括在其主表面上形成的第一导电类型的第一外延层的半导体衬底（ b）掺杂较低带隙杂质，以在掺杂到单元区域内的第一外延层之后使带隙小于第一外延层的带隙，从而形成较低带隙区域，（c）在步骤 （b）中，形成与第一导电类型相反的导电类型的多个第一导电类型的第一列区域，以便在从单元区域扩展到第一导电类型的第一外延层中彼此分离 周边区域，（d）在步骤（c）之后，形成第二外延层。

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