公开(公告)号：US10432389B2

公开(公告)日：2019-10-01

申请号：US15949898

申请日：2018-04-10

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian Leibowitz ,  Jaeha Kim ,  Jafar Savoj

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/06 ,  G06Q10/06 ,  G06Q10/10 ,  H04L25/03 ,  H04L27/00

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

公开(公告)号：US10044530B2

公开(公告)日：2018-08-07

申请号：US15178493

申请日：2016-06-09

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

IPC: H03H7/30 ,  H04B1/10 ,  H04L25/03 ,  G06F13/38

Abstract: An integrated circuit (IC) memory controller includes receiver circuitry to receive read data from a memory. The receiver circuitry includes equalization circuitry having at least one tap to apply data level equalization to the read data, and a tap weight adapter circuit. The tap weight adapter circuit adaptively generates a data level tap weight corresponding to the data level equalization from an edge analysis of previously received read data.

公开(公告)号：US09973328B2

公开(公告)日：2018-05-15

申请号：US15209529

申请日：2016-07-13

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian Leibowitz ,  Jaeha Kim ,  Jafar Savoj

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/06 ,  G06Q10/06 ,  G06Q10/10 ,  H04L25/03 ,  H04L27/00

CPC classification number: H04L7/0016 ,  G06Q10/06312 ,  G06Q10/103 ,  H04L7/0004 ,  H04L7/0062 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/062 ,  H04L2025/0349 ,  H04L2027/004 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

公开(公告)号：US09912469B2

公开(公告)日：2018-03-06

申请号：US15369806

申请日：2016-12-05

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jared L. Zerbe ,  Carl William Werner

IPC: H04L7/027 ,  H04L7/033 ,  H03L7/091 ,  H04L7/00 ,  H03L7/081

CPC classification number: H04L7/0278 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337 ,  H04L7/0338

Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

公开(公告)号：US20180052194A1

公开(公告)日：2018-02-22

申请号：US15699874

申请日：2017-09-08

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jaeha Kim ,  Brian Liebowitz

IPC: G01R29/26 ,  G01R31/317

CPC classification number: G01R29/26 ,  G01R31/31709 ,  G01R31/31725

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

公开(公告)号：US09900189B2

公开(公告)日：2018-02-20

申请号：US15233557

申请日：2016-08-10

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US09791492B2

公开(公告)日：2017-10-17

申请号：US15209494

申请日：2016-07-13

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jaeha Kim ,  Brian Liebowitz

IPC: H04L7/00 ,  G01R29/26 ,  G01R31/317

CPC classification number: G01R29/26 ,  G01R31/31709 ,  G01R31/31725

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

公开(公告)号：US20170052221A1

公开(公告)日：2017-02-23

申请号：US15209494

申请日：2016-07-13

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jaeha Kim ,  Brian Liebowitz

IPC: G01R29/26 ,  G01R31/317

CPC classification number: G01R29/26 ,  G01R31/31709 ,  G01R31/31725

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

Abstract translation: 能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样 。 从接收器输出的采样数据值用于评估集成电路的抖动容限。

公开(公告)号：US09515814B2

公开(公告)日：2016-12-06

申请号：US14820266

申请日：2015-08-06

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jared L. Zerbe ,  Carl William Werner

IPC: H04L7/033 ,  H03L7/081 ,  H03L7/091 ,  H04L7/00

CPC classification number: H04L7/0278 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337 ,  H04L7/0338

Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

公开(公告)号：US09391816B2

公开(公告)日：2016-07-12

申请号：US14462561

申请日：2014-08-19

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

IPC: H03H7/30 ,  H04B1/10 ,  H04L27/06 ,  H04L7/00 ,  H04L25/03

CPC classification number: H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

Abstract: A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

Abstract translation: 公开了一种方法。 该方法包括对数据信号的预期边沿时间具有电压值的数据信号进行采样。 产生第一个α值，并根据电压值生成第二个alpha值。 数据信号通过第一个alpha值进行调整，以得到第一个调整后的信号。 数据信号通过第二α值进行调整，以得到第二调整信号。 第一调整后的信号被采样以输出第一数据值，而第二调整信号被采样以输出第二数据值。 作为先前接收的数据值的函数，在第一数据值和第二数据值之间进行选择，以确定接收到的数据值。