公开(公告)号：US20130093044A1

公开(公告)日：2013-04-18

申请号：US13707150

申请日：2012-12-06

Applicant: Renesas Electronics Corporation

Inventor： Hiroaki OHKUBO ,  Yasutaka NAKASHIBA

IPC: H01L23/525

CPC classification number: H01L23/5252 ,  G11C17/143 ,  G11C17/16 ,  G11C29/027 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.

Abstract translation: 半导体器件包括信号输出单元和判定单元。 信号输出单元包括m（> = 2）个保险丝，NAND门，电阻元件和输出端。 决定单元判定在信号输出单元中包括的m个熔丝中是否断开了n个以上的熔丝（m> = n> = 2），并输出判定结果。 当m = n = 2时，判定单元由具有连接到保险丝的相应端的两个输入端的NOR门构成。 因此，当判定结果为肯定时，在或非门的输出端输出H电平电位信号。 另一方面，当判定结果为负时，在输出端输出L电平电位信号。

公开(公告)号：US20240312969A1

公开(公告)日：2024-09-19

申请号：US18588091

申请日：2024-02-27

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Tatsuo KASAOKA ,  Yasutaka NAKASHIBA

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/162 ,  H01L24/48 ,  H01L2224/48195 ,  H01L2924/1206

Abstract: A semiconductor chip includes a semiconductor substrate and a multilayer wiring layer formed on the semiconductor substrate, and at least one layer of the multilayer wiring layer is formed with a conductive pattern. The conductive pattern is formed so as to continuously surround a lower inductor and an upper inductor in plan view.

公开(公告)号：US20240162144A1

公开(公告)日：2024-05-16

申请号：US18510633

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Yasutaka NAKASHIBA ,  Tatsuo KASAOKA

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01L24/05 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/48464 ,  H01L2924/30101

Abstract: A semiconductor device includes a semiconductor substrate, a multilayer wiring layer formed on the semiconductor substrate, a first wiring formed on the multilayer wiring layer and configured to be applied with a first potential, an upper inductor formed on the multilayer wiring layer and configured to be applied with a second potential different from the first potential, an inorganic insulating film formed on the multilayer wiring layer, the first wiring, and the upper inductor, and an organic insulating film formed on the inorganic insulating film and disposed so as to cover the inorganic insulating film located between the first wiring and the upper inductor in plan view. Here, between the first wiring and the upper inductor, an opening portion exposing a part of the upper surface of the inorganic insulating film is formed in the organic insulating film.

公开(公告)号：US20240096788A1

公开(公告)日：2024-03-21

申请号：US18344431

申请日：2023-06-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki IGARASHI ,  Tatsuo KASAOKA ,  Yasutaka NAKASHIBA

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5227 ,  H01L23/5283 ,  H01L23/53257

Abstract: A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.

公开(公告)号：US20230369278A1

公开(公告)日：2023-11-16

申请号：US17742975

申请日：2022-05-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Toshiyuki HATA

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L24/33 ,  H01L23/3157 ,  H01L24/06 ,  H01L24/73 ,  H01L24/05 ,  H01L24/02 ,  H01L25/16 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05083 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0615 ,  H01L2224/2919 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/45124 ,  H01L24/46 ,  H01L2224/46 ,  H01L24/48 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49175 ,  H01L2224/49171 ,  H01L2224/49177 ,  H01L24/49 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2224/0221 ,  H01L2224/02215 ,  H01L2924/13091 ,  H01L29/7813

Abstract: A semiconductor device includes: a first semiconductor chip mounted on a chip mounting portion via a first bonding material; and a second semiconductor chip mounted on the first semiconductor chip. Here, the first semiconductor chip has: a protective film located in an uppermost layer; and a first pad electrode exposed from the protective film at an inside of a first opening portion of the protective film. Also, the second semiconductor chip is mounted on a conductive material, which is arranged on the first pad electrode of the first semiconductor chip, via a second bonding material of an insulative property.

公开(公告)号：US20230275069A1

公开(公告)日：2023-08-31

申请号：US18059583

申请日：2022-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi YANAGIGAWA ,  Yasutaka NAKASHIBA ,  Toshiyuki HATA

IPC: H01L25/065 ,  H01L23/495 ,  H01L23/498 ,  H01L23/482

CPC classification number: H01L25/0657 ,  H01L23/4828 ,  H01L23/49572 ,  H01L23/49844

Abstract: A semiconductor device includes a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed on a first front surface of the first semiconductor chip, and a first drain electrode is formed on a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed on a second front surface of the second semiconductor chip, and a second drain electrode is formed on a second back surface of the second semiconductor chip. The first back surface and the second back surface are faced to each other such that the first drain electrode and the second drain electrode are in contact with each other via a conductive tape.

公开(公告)号：US20230134000A1

公开(公告)日：2023-05-04

申请号：US17887094

申请日：2022-08-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki SEKIKAWA ,  Yasutaka NAKASHIBA ,  Hideki SASAKI ,  Hajime HAYASHIMOTO

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a clip which is electrically connected to a main-transistor source pad via a first silver paste and is connected to a lead via a second silver paste. The clip has a “first part” with which the first silver paste is in contact, a “second part” with which the second silver paste is in contact, and a “third part” positioned between the “first part” and the “second part”. A protruding member is formed on a surface of the main-transistor source pad, and the “first part” is in contact with the protruding member.

公开(公告)号：US20230113513A1

公开(公告)日：2023-04-13

申请号：US17886024

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsunori TSUNETSUGU ,  Yasutaka NAKASHIBA

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/495 ,  H01L23/528

Abstract: A multilayer wiring structure in which a plurality of conductive films and a plurality of interlayer dielectric films are laminated is formed so as to cover a main surface of a first semiconductor chip. The conductive films include conductive films to which a low voltage is applied and conductive films to which a high voltage is applied. The conductive films to which the low voltage is applied are located below the conductive films to which the high voltage is applied and closer to the main surface of a semiconductor substrate. The conductive films are arranged as conductive films of at least one layer between a first inductor to which the low voltage is applied and a second inductor to which the high voltage is applied.

公开(公告)号：US20220173056A1

公开(公告)日：2022-06-02

申请号：US17108298

申请日：2020-12-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA

IPC: H01L23/64 ,  H01F27/00

Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.

公开(公告)号：US20210302801A1

公开(公告)日：2021-09-30

申请号：US16829509

申请日：2020-03-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro KUWAJIMA ,  Yasutaka NAKASHIBA

IPC: G02F1/225 ,  G02F1/025

Abstract: A semiconductor device includes a first insulating layer, an optical modulator, and a multilayer wiring layer. The optical modulator is formed on the first insulating layer. The multilayer wiring layer is formed on the first insulating layer and including a wiring and a resistive element which are spaced apart from each other. The resistive element is formed without overlapping with the optical modulator in plan view. A material of the resistive element is at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and silicon chromium.