公开(公告)号：US20160267011A1

公开(公告)日：2016-09-15

申请号：US14732654

申请日：2015-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0877 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/16 ,  G06F2212/60 ,  G06F2212/7203

Abstract: A Solid State Drive (SSD) is disclosed. The SSD can include a host interface logic, a data input buffer, a data output buffer, and a buffer manager to manage the data input buffer and data output buffer. A re-order logic can advise the buffer manager about which data should be returned to the host computer from the data output buffer.

Abstract translation: 公开了固态硬盘（SSD）。 SSD可以包括主机接口逻辑，数据输入缓冲器，数据输出缓冲器和缓冲器管理器，以管理数据输入缓冲器和数据输出缓冲器。 重新排序逻辑可以建议缓冲管理器应该从数据输出缓冲区向主计算机返回哪些数据。

公开(公告)号：US20160266975A1

公开(公告)日：2016-09-15

申请号：US14863446

申请日：2015-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaohong HU ,  Hongzhong ZHENG ,  Dimin NIU

IPC: G06F11/10 ,  G06F12/10 ,  G06F3/06

CPC classification number: G06F12/1009 ,  G06F11/1048 ,  G06F12/0246 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/65 ,  G06F2212/7201

Abstract: An embodiment includes a system, comprising: an Error Correcting Code (ECC) memory comprising a plurality of memory locations, each memory location corresponding to a device address of the ECC memory; a system management bus (SMB); a baseboard management controller (BMC) coupled to the ECC memory through the SMB; and an operating system comprising a driver module coupled to the BMC through the SMB, the driver module being configured to receive through the Memory device address information associated with the ECC memory and to convert the device address information into physical address information independent of an ECC memory controller.

Abstract translation: 一个实施例包括一种系统，包括：纠错码（ECC）存储器，包括多个存储器位置，每个存储器位置对应于ECC存储器的设备地址; 系统管理总线（SMB）; 通过SMB耦合到ECC存储器的基板管理控制器（BMC）; 以及操作系统，其包括通过所述SMB耦合到所述BMC的驱动器模块，所述驱动器模块被配置为通过所述存储器设备接收与所述ECC存储器相关联的地址信息，并将所述设备地址信息转换为独立于ECC存储器的物理地址信息 控制器。

公开(公告)号：US20240143173A1

公开(公告)日：2024-05-02

申请号：US18408558

申请日：2024-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/106 ,  G11C29/52 ,  G11C5/04

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

公开(公告)号：US20200184001A1

公开(公告)日：2020-06-11

申请号：US16388860

申请日：2019-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Peng GU ,  Krishna MALLADI ,  Hongzhong ZHENG ,  Dimin NIU

IPC: G06F17/16 ,  G06F12/0877

Abstract: A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.

公开(公告)号：US20200167297A1

公开(公告)日：2020-05-28

申请号：US16777206

申请日：2020-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  lndong KIM ,  Jangseok CHOI ,  Craig HANSON

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20190266049A1

公开(公告)日：2019-08-29

申请号：US16411122

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Hyun-Joong KIM ,  Won-Hyung SONG ,  Jangseok CHOI

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4093

Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

公开(公告)号：US20180322007A1

公开(公告)日：2018-11-08

申请号：US15675679

申请日：2017-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F13/4239

Abstract: A hardware coding mechanism is described. The coding mechanism may include a first encoder to produce a first code using a base number of bits and a second encoder to produce a second code using a supplementary number of bits. The second code and the first code together may be stronger than the first code alone. A mode register stored in a storage may specify whether a switch to the second encoder is open or closed: the first coder is always used.

公开(公告)号：US20180144786A1

公开(公告)日：2018-05-24

申请号：US15812497

申请日：2017-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Young LIM ,  In-Su CHOI ,  Dimin NIU ,  In-Dong KIM

IPC: G11C11/4096 ,  G06F11/20 ,  G06F11/10 ,  G11C29/52

Abstract: A memory system may comprise a plurality of data strobe transfer paths assigned to a plurality of data transfer paths such that each of the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths. At least one selected data strobe transfer path is selected and data signals transferred through the plurality of data transfer paths are sampled using at least one data strobe signal transferred through the selected data strobe transfer path. Reliability of data communication is enhanced through a redundant data strobe scheme by assigning a plurality of data strobe transfer paths to a plurality of data transfer paths such that the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths.

公开(公告)号：US20170365305A1

公开(公告)日：2017-12-21

申请号：US15231629

申请日：2016-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Craig HANSON ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G11C7/10 ,  G06F1/32

CPC classification number: G11C7/1072 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/04 ,  G11C5/148 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4074 ,  G11C2207/2227 ,  Y02D10/14 ,  Y02D50/20

Abstract: A memory module includes a plurality of memory components, an in-memory power manager, and an interface to a host computer over a memory bus. The in-memory power manager is configured to control a transition of a power state of the memory module. The transition of the power state of the memory module includes a direct transition from a low power down state to a maximum power down state.

公开(公告)号：US20220035719A1

公开(公告)日：2022-02-03

申请号：US17499852

申请日：2021-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Krishna MALLADI ,  Hongzhong ZHENG

IPC: G06F11/20 ,  G06F11/10

Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.