公开(公告)号：US09099470B2

公开(公告)日：2015-08-04

申请号：US14208456

申请日：2014-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L21/033 ,  H01L23/528 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L27/115 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US09093454B2

公开(公告)日：2015-07-28

申请号：US14186617

申请日：2014-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/115

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US09064734B2

公开(公告)日：2015-06-23

申请号：US13668883

申请日：2012-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/823468 ,  H01L27/11521 ,  H01L29/66825

Abstract: A semiconductor device includes a substrate including an active region and a field region, first gate structures disposed on the active region, first air gaps disposed between the first gate structures, second gate structures disposed on the field region, second air gaps disposed between the second gate structures, and an interlayer insulating layer disposed on the first gate structures, the first air gaps, the second gate structures, and the second air gaps. A lowermost level of the second air gaps is lower than a lowermost level of the first gate structures.

Abstract translation: 半导体器件包括：衬底，其包括有源区和场区;布置在有源区上的第一栅极结构，设置在第一栅极结构之间的第一气隙，设置在场区上的第二栅极结构， 栅极结构和设置在第一栅极结构，第一气隙，第二栅极结构和第二气隙上的层间绝缘层。 第二气隙的最低水平低于第一门结构的最低水平。

公开(公告)号：US09006814B2

公开(公告)日：2015-04-14

申请号：US14290234

申请日：2014-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim

IPC: H01L29/788 ,  H01L29/792 ,  H01L43/02 ,  H01L27/22 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/228 ,  H01L29/7881 ,  H01L29/792 ,  H01L43/02

Abstract: A semiconductor memory device includes a substrate including a cell region and a peripheral region, word lines on the substrate of the cell region, each of the word lines including a charge storing part and a control gate electrode sequentially stacked, and a peripheral gate pattern on the substrate of the peripheral region. Each of the control gate electrode and the peripheral gate pattern includes a high-carbon semiconductor pattern and a low-carbon semiconductor pattern, the low-carbon semiconductor pattern being on the high-carbon semiconductor pattern.

Abstract translation: 半导体存储器件包括：包括单元区域和外围区域的衬底，单元区域的衬底上的字线，每个字线包括依次堆叠的电荷存储部分和控制栅电极;以及周边栅极图案， 外围区域的基板。 控制栅电极和外围栅极图案中的每一个包括高碳半导体图案和低碳半导体图案，低碳半导体图案位于高碳半导体图案上。

公开(公告)号：US08975684B2

公开(公告)日：2015-03-10

申请号：US13915158

申请日：2013-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  HoJun Seong

IPC: H01L29/06 ,  H01L21/764 ,  H01L29/788 ,  H01L27/115 ,  H01L21/762

CPC classification number: H01L27/11521 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11563 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/7881

Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

Abstract translation: 公开了非易失性存储器件及其制造方法。 非易失性存储器件包括限定衬底中的有源部分和设置在衬底上的栅极结构的器件隔离图案。 有源部分在第一方向上彼此间隔开，并且在垂直于第一方向的第二方向上延伸。 栅极结构在第二方向上彼此间隔开并且在第一方向上延伸。 每个器件隔离图案包括第一气隙，并且第一气隙的顶表面和底表面中的每一个在沿着第二方向截取的截面图中具有波形。

公开(公告)号：US08969215B2

公开(公告)日：2015-03-03

申请号：US14079282

申请日：2013-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwang Sim ,  Jinhyun Shin

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/115

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/11519

Abstract: Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby are provided. Two photolithography processes and two spacer processes are performed to provide final patterns that have a pitch that is smaller than a limitation of photolithography process. Furthermore, since initial patterns are formed to have line and pad portions simultaneously by performing a first photolithography process, there is no necessity to perform an additional photolithography process for forming the pad portion.

Abstract translation: 提供制造半导体器件的方法和由此制造的半导体器件。 执行两个光刻工艺和两个间隔器工艺以提供具有小于光刻工艺限制的间距的最终图案。 此外，由于通过执行第一光刻工艺来形成初始图案以同时具有线和焊盘部分，因此不需要执行用于形成焊盘部分的附加光刻工艺。

公开(公告)号：US20140273495A1

公开(公告)日：2014-09-18

申请号：US14293346

申请日：2014-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minchul Kim ,  Jae-Hwang Sim ,  Sangbin Song

IPC: H01L21/3213 ,  H01L29/66

CPC classification number: H01L21/32135 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: A non-volatile memory device comprises a substrate, a control gate electrode on the substrate, and a charge storage region between the control gate electrode and the substrate. A control gate mask pattern is on the control gate electrode, the control gate electrode comprising a control base gate and a control metal gate on the control base gate. A width of the control metal gate is less than a width of the control gate mask pattern. An oxidation-resistant spacer is at sidewalls of the control metal gate positioned between the control gate mask pattern and the control base gate.

Abstract translation: 非易失性存储器件包括衬底，衬底上的控制栅极电极和控制栅电极与衬底之间的电荷存储区域。 控制栅极掩模图案位于控制栅电极上，控制栅极电极包括控制基极栅极和控制基极栅极上的控制金属栅极。 控制金属栅极的宽度小于控制栅极掩模图案的宽度。 位于控制栅掩模图案和控制基栅之间的控制金属栅极的侧壁处具有抗氧化间隔物。

公开(公告)号：US20140154885A1

公开(公告)日：2014-06-05

申请号：US14079282

申请日：2013-11-13

Applicant: Samsung Electronics Co., Ltd

Inventor： Jae-Hwang Sim ,  Jinhyun Shin

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/11519

Abstract: Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby are provided. Two photolithography processes and two spacer processes are performed to provide final patterns that have a pitch that is smaller than a limitation of photolithography process. Furthermore, since initial patterns are formed to have line and pad portions simultaneously by performing a first photolithography process, there is no necessity to perform an additional photolithography process for forming the pad portion.

Abstract translation: 提供制造半导体器件的方法和由此制造的半导体器件。 执行两个光刻工艺和两个间隔器工艺以提供具有小于光刻工艺限制的间距的最终图案。 此外，由于通过执行第一光刻工艺来形成初始图案以同时具有线和焊盘部分，因此不需要执行用于形成焊盘部分的附加光刻工艺。

公开(公告)号：US08741767B2

公开(公告)日：2014-06-03

申请号：US14091680

申请日：2013-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonmoon Park ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

IPC: H01L23/48 ,  H01L27/32

CPC classification number: H01L27/3223 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

Abstract translation: 半导体器件包括：半导体衬底，包括单元区域和与单元区域相邻的芯区域，单元区域和芯区域中的有源区域，覆盖有源区域的层间绝缘层，穿过层间绝缘层的上部单元触点 电池区域，上电池触点沿着第一方向彼此相邻并且电连接到有源区域，并且芯触点穿透芯区域的有源区域中的层间绝缘层，芯触点与每个区域相邻 另一个沿着第一方向并且包括电连接到有源区的上连接芯触点，以及与上连接芯触点相邻的虚拟触头，虚拟触头与有源区绝缘。

公开(公告)号：US20240074192A1

公开(公告)日：2024-02-29

申请号：US18202019

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Yoon Kim ,  Byoung Jae Park ,  Jae-Hwang Sim ,  Jongseon Ahn ,  Young-Ho Lee

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06524

Abstract: A three-dimensional semiconductor device includes: a source structure including a cell region and an extension region; a gate stacking structure disposed on the source structure, the gate stacking structure including insulating patterns and conductive patterns, which are alternately stacked on each other; an insulating structure disposed on the gate stacking structure, the insulating structure including a plurality of insulating layers; a memory channel structure penetrating the gate stacking structure and electrically connected to the cell region; a separation structure penetrating the gate stacking structure and extending from the cell region to the extension region; and a penetration plug penetrating the gate stacking structure and the extension region, wherein the penetration plug includes: a first plug portion penetrating the gate stacking structure; and a second plug portion on the first plug portion, wherein the separation structure includes: a first separation portion penetrating the gate stacking structure; and a second separation portion on the first separation portion, and wherein a top surface of the first plug portion and a top surface of the first separation portion are at a substantially same level.