公开(公告)号：US11832925B2

公开(公告)日：2023-12-05

申请号：US16797574

申请日：2020-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hansung Lee ,  Chansoo Park ,  Hyunsu Hong ,  Sander Land ,  Jongho Park ,  Hyejung Seo ,  Yongjin Lee

IPC: A61B5/0295 ,  A61B5/024 ,  A61B5/1455 ,  A61B5/00

CPC classification number: A61B5/0295 ,  A61B5/02433 ,  A61B5/14551 ,  A61B5/4818 ,  A61B5/681 ,  A61B5/6843 ,  A61B5/7221

Abstract: An electronic device includes a housing, a touchscreen display viewable through a first part of the housing, a photoplethysmogram (PPG) sensor exposed through a second part of the housing, a processor disposed in the housing and operatively connected to the touchscreen display and the PPG sensor, and a memory disposed in the housing and operatively connected to the processor, wherein the memory stores instructions that, when executed, are configured to cause the processor to receive first data from the PPG sensor, generate second data by band-pass filtering the first data, generate oxygen saturation data based on at least some of the second data, select a first portion related to a first period of time from the second data, and display, on the touchscreen display, a graphical user interface including information related to the oxygen saturation data except for data corresponding to the first portion from the graphical user interface.

公开(公告)号：US11728142B2

公开(公告)日：2023-08-15

申请号：US16883392

申请日：2020-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Jaeho Kwak ,  Boeun Jang ,  Seokyeon Hwang ,  Yongseok Seo ,  Sangsoo Kim ,  Seunghwan Kim ,  Jongho Park ,  Yongkwan Lee ,  Jongho Lee ,  Daewook Kim ,  Wonpil Lee ,  Changkyu Choi

IPC: H01J37/32 ,  C23C16/455 ,  C23C16/458 ,  H01L21/673

CPC classification number: H01J37/32449 ,  C23C16/45504 ,  C23C16/45589 ,  H01J37/32633 ,  C23C16/4583 ,  C23C16/45502 ,  C23C16/45591 ,  H01J37/32357 ,  H01L21/67326

Abstract: A surface treatment apparatus and a surface treatment system having the same are disclosed. The surface treatment apparatus includes a process chamber in which the surface treatment process is conducted, a plasma generator for generating process radicals as a plasma state for the surface treatment process, the plasma generator being positioned outside of the process chamber and connected to the process chamber by a supply duct, a heat exchanger arranged on the supply duct and cooling down temperature of the process radicals passing through the supply duct and a flow controller controlling the process radicals to flow out of the process chamber. The flow controller is connected to a discharge duct through which the process radicals are discharged outside the process chamber. The plasma surface treatment process is conducted to the package structure having minute mounting gap without the damages to the IC chip and the board.

公开(公告)号：US11610845B2

公开(公告)日：2023-03-21

申请号：US17392705

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Seung Hwan Kim ,  Jun Young Oh ,  Kyong Hwan Koh ,  Sangsoo Kim ,  Dong-Ju Jang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/16 ,  H01L23/31

Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.

公开(公告)号：US20220238539A1

公开(公告)日：2022-07-28

申请号：US17723523

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Musarrat Hasan ,  Wandon Kim ,  Seungkeun Cha

IPC: H01L27/1159 ,  H01L29/78 ,  H01L27/11585 ,  H01L29/51

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.

公开(公告)号：US20210408260A1

公开(公告)日：2021-12-30

申请号：US17470102

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Park ,  Byounghoon Lee ,  Seungkeun Cha ,  Wandon Kim

IPC: H01L29/49 ,  H01L29/45 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

Abstract: Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal.

公开(公告)号：US11107769B2

公开(公告)日：2021-08-31

申请号：US16845890

申请日：2020-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Seung Hwan Kim ,  Jun Young Oh ,  Kyong Hwan Koh ,  Sangsoo Kim ,  Dong-Ju Jang

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/16 ,  H01L25/065

Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.

公开(公告)号：US11062116B2

公开(公告)日：2021-07-13

申请号：US16173704

申请日：2018-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho Yun ,  Yongjin Lee ,  Hyunseok Shin ,  Jongho Park ,  Seungeun Lee

IPC: G06K9/00 ,  G16H10/60 ,  A61B5/00 ,  G16H40/63 ,  A61B5/1455 ,  A61B5/16

Abstract: An electronic device includes a light emitting unit, including a first light emitting element and a second light emitting element; and a plurality of light receiving units disposed in a structure that encloses the light emitting unit, wherein the first light emitting element and the second light emitting element are disposed in a separated state based on a radiation area related to the light emitting unit in a designated distance range. Various embodiments are available.

公开(公告)号：US20250149467A1

公开(公告)日：2025-05-08

申请号：US18917246

申请日：2024-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juil Choi ,  Jongho Park ,  Chanwook Park ,  Hyungjun Park ,  Taeoh Ha ,  Hongseo Heo

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a first die structure including a support substrate having a cavity, a first semiconductor chip in the cavity, and a first gap filling layer that fills a gap between an inner wall of the cavity and the first semiconductor chip; and a second die structure on the first die structure, the second die structure including a second semiconductor chip and a second gap filling layer surrounding an outer side surface of the second semiconductor chip. The first semiconductor chip includes a first backside insulating layer with second bonding pads. The second semiconductor chip includes a second front insulating layer with third bonding pads. The second bonding pads and the third bonding pads are directly bonded to each other.

公开(公告)号：US11974838B2

公开(公告)日：2024-05-07

申请号：US16964087

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hansung Lee ,  Hwan Shim ,  Yongjin Lee ,  Jooman Han ,  Jongho Park ,  Gahee Jung ,  Seounghun Kim ,  Jihwan Kim ,  Choonghee Ahn ,  Hyungjoon Lim ,  Jiwoon Jung ,  Jeongmin Park

IPC: A61B5/024 ,  A61B5/00 ,  A61B5/0255 ,  A61B5/021

CPC classification number: A61B5/02416 ,  A61B5/02427 ,  A61B5/0255 ,  A61B5/721 ,  A61B5/02108 ,  A61B5/02433 ,  A61B2562/0219 ,  A61B2562/0238

Abstract: An electronic device may include a PPG sensor including a light emitter that applies a current in a specified range and emits a light signal corresponding to the current and a light detector that amplifies a received light signal by applying one of a plurality of gain values, a memory that stores a plurality of sets of PPG models corresponding to the plurality of gain values and including a current value and PPG level data corresponding to the current value, and at least one processor electrically connected to the PPG sensor and the memory.

公开(公告)号：US11778835B2

公开(公告)日：2023-10-03

申请号：US17723523

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Musarrat Hasan ,  Wandon Kim ,  Seungkeun Cha

IPC: H10B51/30 ,  H01L29/78 ,  H01L29/51 ,  H10B51/00

CPC classification number: H10B51/30 ,  H01L29/511 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/00

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.