公开(公告)号：US11610838B2

公开(公告)日：2023-03-21

申请号：US17367773

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuichiro Sasaki ,  Sungkeun Lim ,  Pil-Kyu Kang ,  Weonhong Kim ,  Seungha Oh ,  Yongho Ha ,  Sangjin Hyun

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

公开(公告)号：US11177286B2

公开(公告)日：2021-11-16

申请号：US16807410

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong Kim ,  Pilkyu Kang ,  Yuichiro Sasaki ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun ,  Kughwan Kim ,  Seungha Oh

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/762 ,  H01L27/02

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US11121080B2

公开(公告)日：2021-09-14

申请号：US16809788

申请日：2020-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuichiro Sasaki ,  Sungkeun Lim ,  Pil-Kyu Kang ,  Weonhong Kim ,  Seungha Oh ,  Yongho Ha ,  Sangjin Hyun

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

公开(公告)号：US10763335B2

公开(公告)日：2020-09-01

申请号：US16203197

申请日：2018-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Heonbok Lee ,  Chunghwan Shin ,  Youngsuk Chai ,  Sangjin Hyun

IPC: H01L29/423 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having an active pattern therein, a gate electrode extending across the active pattern and a source/drain region on the active pattern laterally adjacent the gate electrode. The device further includes a contact structure including a first contact on the source/drain region, a second contact on the first contact and a spacer on sidewalls of the first and second contacts.

公开(公告)号：US20200035678A1

公开(公告)日：2020-01-30

申请号：US16592330

申请日：2019-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo LEE ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US20190058035A1

公开(公告)日：2019-02-21

申请号：US15955241

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung Cho ,  Dae-Young Kwak ,  Shinhye Kim ,  Koungmin Ryu ,  Sangjin Hyun

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/088

Abstract: A semiconductor device includes active patterns protruding from a substrate and an insulation structure surrounding lower portions of the active patterns. The insulation structure includes an insulation layer conforming to a top surface of the substrate and to sidewalls of the active patterns and a buried insulation pattern on the insulation layer.

公开(公告)号：US20180151376A1

公开(公告)日：2018-05-31

申请号：US15797340

申请日：2017-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Choi ,  Moonkyun Song ,  Yoon Tae Hwang ,  Kyumin Lee ,  Sangjin Hyun

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/324 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L21/3105

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/82345 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.

公开(公告)号：US20150028430A1

公开(公告)日：2015-01-29

申请号：US14317289

申请日：2014-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junehee Lee ,  Sangjin Hyun ,  Jaeyeol Song ,  Hye-Lan Lee

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate electrode on the gate dielectric pattern opposite the substrate. The gate electrode includes a first conductive pattern disposed on the gate dielectric pattern and including aluminum, and a second conductive pattern disposed between the first conductive pattern and the gate dielectric pattern. The second conductive pattern has an aluminum concentration that is higher than an aluminum concentration of the first conductive pattern. The second conductive pattern may be thicker than the first conductive pattern.

Abstract translation: 公开了半导体器件及其制造方法。 半导体器件在衬底上的栅极电介质图案和与衬底相对的栅极电介质图案上的栅极电极。 栅电极包括设置在栅极电介质图案上并包括铝的第一导电图案，以及设置在第一导电图案和栅极电介质图案之间的第二导电图案。 第二导电图案的铝浓度高于第一导电图案的铝浓度。 第二导电图案可以比第一导电图案更厚。

公开(公告)号：US11742351B2

公开(公告)日：2023-08-29

申请号：US17384920

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo Lee ,  Wonkeun Chung ,  Hoonjoo Na ,  Suyoung Bae ,  Jaeyeol Song ,  Jonghan Lee ,  HyungSuk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US11411106B2

公开(公告)日：2022-08-09

申请号：US17176248

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Weonhong Kim ,  Wandon Kim ,  Hyeonjun Baek ,  Sangjin Hyun

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.