公开(公告)号：US11127739B2

公开(公告)日：2021-09-21

申请号：US16028272

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Lan Lee ,  Sang-Bom Kang ,  Jae-Jung Kim ,  Moon-Kyu Park ,  Jae-Yeol Song ,  June-Hee Lee ,  Yong-Ho Ha ,  Sang-Jin Hyun

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/49 ,  H01L29/66 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/51

Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

公开(公告)号：US20150028430A1

公开(公告)日：2015-01-29

申请号：US14317289

申请日：2014-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junehee Lee ,  Sangjin Hyun ,  Jaeyeol Song ,  Hye-Lan Lee

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate electrode on the gate dielectric pattern opposite the substrate. The gate electrode includes a first conductive pattern disposed on the gate dielectric pattern and including aluminum, and a second conductive pattern disposed between the first conductive pattern and the gate dielectric pattern. The second conductive pattern has an aluminum concentration that is higher than an aluminum concentration of the first conductive pattern. The second conductive pattern may be thicker than the first conductive pattern.

Abstract translation: 公开了半导体器件及其制造方法。 半导体器件在衬底上的栅极电介质图案和与衬底相对的栅极电介质图案上的栅极电极。 栅电极包括设置在栅极电介质图案上并包括铝的第一导电图案，以及设置在第一导电图案和栅极电介质图案之间的第二导电图案。 第二导电图案的铝浓度高于第一导电图案的铝浓度。 第二导电图案可以比第一导电图案更厚。

公开(公告)号：US20140203335A1

公开(公告)日：2014-07-24

申请号：US14155579

申请日：2014-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yeol Song ,  June-Hee Lee ,  Hye-Lan Lee ,  Sang-Jin Hyun ,  Sang-Bom Kang

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/1104 ,  H01L29/51 ,  H01L29/6681

Abstract: A semiconductor device includes an insulating film on a substrate and including a trench, a gate insulating film in the trench, a DIT (Density of Interface Trap) improvement film on the gate insulating film to improve a DIT of the substrate, and a first conductivity type work function adjustment film on the DIT improvement film. Related methods of forming semiconductor devices are also disclosed.

Abstract translation: 半导体器件包括在衬底上的绝缘膜，其包括沟槽，沟槽中的栅极绝缘膜，栅极绝缘膜上的DIT（界面陷阱密度）改进膜，​​以改善衬底的DIT，以及第一导电性 DIT改进膜上的工作功能调整膜。 还公开了形成半导体器件的相关方法。

公开(公告)号：US09543300B2

公开(公告)日：2017-01-10

申请号：US15054571

申请日：2016-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Lan Lee ,  Hong-Bae Park ,  Sang-Jin Hyun ,  Yu-Gyun Shin ,  Sug-Hun Hong ,  Hoon-Joo Na ,  Hyung-Seok Hong

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/092 ,  H01L23/485 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/08 ,  H01L29/94

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0811 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

Abstract translation: 提供了CMOS晶体管，具有晶体管的半导体器件和具有该器件的半导体模块。 CMOS晶体管可以包括分别设置在半导体衬底的第一和第二区域中的第一和第二互连结构。 半导体衬底的第一和第二区域可以具有不同的导电类型。 第一和第二互连结构可以设置在半导体衬底上。 第一互连结构可以具有与第二互连结构不同的堆叠结构。 CMOS晶体管可以设置在半导体器件中。 半导体器件可以设置在半导体模块中。

公开(公告)号：USRE49538E1

公开(公告)日：2023-05-30

申请号：US17070488

申请日：2020-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo Na ,  Sangjin Hyun ,  Yugyun Shin ,  Hongbae Park ,  Sughun Hong ,  Hye-Lan Lee ,  Hyung-Seok Hong

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28 ,  H01L29/49 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

公开(公告)号：US20180331100A1

公开(公告)日：2018-11-15

申请号：US16028272

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Lan Lee ,  Sang-Bom Kang ,  Jae-Jung Kim ,  Moon-Kyu Park ,  Jae-Yeol Song ,  June-Hee Lee ,  Yong-Ho Ha ,  Sang-Jin Hyun

IPC: H01L27/088 ,  H01L21/84 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/092 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

公开(公告)号：US09337295B2

公开(公告)日：2016-05-10

申请号：US14317289

申请日：2014-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junehee Lee ,  Sangjin Hyun ,  Jaeyeol Song ,  Hye-Lan Lee

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacturing the same are disclosed. The semiconductor device a gate dielectric pattern on a substrate and a gate electrode on the gate dielectric pattern opposite the substrate. The gate electrode includes a first conductive pattern disposed on the gate dielectric pattern and including aluminum, and a second conductive pattern disposed between the first conductive pattern and the gate dielectric pattern. The second conductive pattern has an aluminum concentration that is higher than an aluminum concentration of the first conductive pattern. The second conductive pattern may be thicker than the first conductive pattern.

Abstract translation: 公开了半导体器件及其制造方法。 半导体器件在衬底上的栅极电介质图案和与衬底相对的栅极电介质图案上的栅极电极。 栅电极包括设置在栅极电介质图案上并包括铝的第一导电图案，以及设置在第一导电图案和栅极电介质图案之间的第二导电图案。 第二导电图案的铝浓度高于第一导电图案的铝浓度。 第二导电图案可以比第一导电图案更厚。

公开(公告)号：US09252058B2

公开(公告)日：2016-02-02

申请号：US14308745

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Seok Hong ,  Sang-Jin Hyun ,  Hong-Bae Park ,  Hoon-Joo Na ,  Hye-Lan Lee

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping.

Abstract translation: 制造半导体器件的方法，半导体器件和结合其的系统包括掺杂有杂质的栅极金属的晶体管。 晶体管的改变的功函数可以改变晶体管的阈值电压。 在某些实施例中，第一MOSFET的栅极金属掺杂有杂质。 第二MOSFET的栅极金属可以不掺杂，掺杂有不同浓度的相同杂质和/或掺杂有不同杂质。 在一些实施例中，MOSFET是FinFET，并且掺杂可以是共形掺杂。

公开(公告)号：US20140302652A1

公开(公告)日：2014-10-09

申请号：US14308745

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Seok Hong ,  Sang-Jin Hyun ,  Hong-Bae Park ,  Hoon-Joo Na ,  Hye-Lan Lee

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping

Abstract translation: 制造半导体器件的方法，半导体器件和结合其的系统包括掺杂有杂质的栅极金属的晶体管。 晶体管的改变的功函数可以改变晶体管的阈值电压。 在某些实施例中，第一MOSFET的栅极金属掺杂有杂质。 第二MOSFET的栅极金属可以不掺杂，掺杂有不同浓度的相同杂质和/或掺杂有不同杂质。 在一些实施例中，MOSFET是FinFET，并且掺杂可以是共形掺杂

公开(公告)号：US08766366B2

公开(公告)日：2014-07-01

申请号：US13633663

申请日：2012-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo Na ,  Sangjin Hyun ,  Yugyun Shin ,  Hongbae Park ,  Sughun Hong ,  Hye-Lan Lee ,  Hyung-seok Hong

IPC: H01L29/49

CPC classification number: H01L21/823842 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

Abstract translation: 制造半导体器件的方法包括在衬底上形成层间电介质，所述层间电介质包括分别设置在所述衬底中分开形成的第一和第二区域中的第一和第二开口; 形成填充所述第一和第二开口的第一导电层; 蚀刻第一导电层，使得第一开口的底表面露出，并且第二开口中的第一导电层的一部分保留; 以及形成填充所述第一开口和所述第二开口的一部分的第二导电层。