公开(公告)号：US20140256101A1

公开(公告)日：2014-09-11

申请号：US14281482

申请日：2014-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Chang MOON ,  Sung-Min HWANG ,  Woonkyung LEE

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L29/7926

Abstract: A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.

Abstract translation: 三维半导体存储器件具有层叠结构，其包括彼此绝缘的单元栅极和彼此横向分离的第一串选择栅极，延伸穿过第一串选择栅极的垂直有源图案，侧壁之间的多层电介质层 垂直有源图案和单元栅极之间以及垂直有源图案和第一串选择栅极的侧壁之间以及至少一个第一补充导电图案。 第一串选择栅极设置在单元栅极的最上面的单元栅极上。 每个垂直有源图案延伸穿过堆叠在第一串选择门下的每个单元门。 第一补充导电图案与第一串选择门之一的侧壁接触。

公开(公告)号：US20240090211A1

公开(公告)日：2024-03-14

申请号：US18135349

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soyeon KIM ,  Sung-Min HWANG ,  Dong-Sik LEE ,  Seunghyun CHO ,  Bongtae PARK ,  Jae-Joo SHIM

IPC: H10B41/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor memory device includes a gate stack structure including insulating layers, a lower selection line and word lines, the word lines including a first word line adjacent to the lower selection line and a second word line on the first word line, a memory channel structure penetrating the gate stack structure, a plurality of first contact plugs electrically connected to the first word line, a plurality of second contact plugs electrically connected to the second word line, a first conductive line connected to the plurality of first contact plugs, and a second conductive line connected to one of the plurality of second contact plugs.

公开(公告)号：US20230094302A1

公开(公告)日：2023-03-30

申请号：US17747412

申请日：2022-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Dongsung WOO ,  Tae Gon LEE ,  Bongtae PARK ,  Jae-Joo SHIM ,  Tae-Chul JUNG

IPC: H01L27/11526 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device and an electronic system including the same are disclosed. The semiconductor device may include a substrate including a cell array region and a connection region, the cell array region comprising a center region and an outer region; an electrode structure including electrodes and pads; vertical structures on the cell array region and penetrating the electrode structure; and a separation insulating pattern penetrating and dividing an upper electrode, which is one of the electrodes, into at least two portions arranged in a second direction crossing the first direction. The separation insulating pattern comprises a first portion and a second portion, the first portion is between at least some of the central vertical structures, and the second portion is spaced apart from the first portion such that, when viewed in the plan view, the second portion is between at least some of the peripheral vertical structure.

公开(公告)号：US20220375959A1

公开(公告)日：2022-11-24

申请号：US17552812

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangdon LEE ,  Jiwon KIM ,  Sung-Min HWANG ,  Sukkang SUNG

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11573

Abstract: Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. The device includes a substrate, a cell array structure provided on the substrate to include a plurality of stacked electrodes spaced apart from each other, an uppermost one of the electrodes being a first string selection line, a vertical channel structure provided to penetrate the cell array structure and connected to the substrate, a conductive pad provided in an upper portion of the vertical channel structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a cutting structure penetrating the first string selection line. The cutting structure penetrates a portion of the conductive pad. A bottom surface of the bit line contact includes first and second bottom surfaces in contact with the conductive pad and the cutting structure, respectively.

公开(公告)号：US20220246643A1

公开(公告)日：2022-08-04

申请号：US17726899

申请日：2022-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho AHN ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Bum Kyu KANG ,  Sang Don LEE

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556

Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

公开(公告)号：US20220115344A1

公开(公告)日：2022-04-14

申请号：US17405637

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Won KIM ,  Jae Ho AHN ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Suk Kang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

公开(公告)号：US20220028885A1

公开(公告)日：2022-01-27

申请号：US17203122

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Young KIM ,  Woo Sung YANG ,  Sung-Min HWANG ,  Suk Kang SUNG ,  Joon-Sung LIM

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

公开(公告)号：US20210098478A1

公开(公告)日：2021-04-01

申请号：US16858983

申请日：2020-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Woosung YANG ,  Joon-Sung LIM ,  Jiyoung KIM ,  Jiwon KIM

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  G11C5/06 ,  H01L23/528

Abstract: Disclosed is a three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, a stack including first and second stacks sequentially stacked on the substrate, the stack having a staircase structure on the connection region, each of the first and second stacks including conductive patterns vertically stacked on the substrate, and contact plugs disposed on the connection region and respectively coupled to the conductive patterns. A bottom surface of each contact plug is located between top and bottom surfaces of a corresponding conductive pattern. In each stack, a recess depth of each contact plug varies monotonically in a stacking direction of the conductive patterns, when measured from a top surface of a corresponding conductive pattern. The contact plugs coupled to an uppermost conductive pattern of the first stack and a lowermost conductive pattern of the second stack have discrete recess depths.

公开(公告)号：US20200303284A1

公开(公告)日：2020-09-24

申请号：US16722418

申请日：2019-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Sung YANG ,  Joon-Sung LIM ,  Sung-Min HWANG ,  Ji-Young KIM ,  Ji-Won KIM

IPC: H01L23/48 ,  H01L27/11575 ,  H01L27/11582

Abstract: A vertical semiconductor device including a plurality of vertical memory cells on an upper surface of a first substrate, an adhesive layer on a lower surface of the first substrate that is opposite to the upper surface of the first substrate, a second substrate having first peripheral circuits thereon, a lower insulating interlayer on the second substrate, and a plurality of wiring structures electrically connecting the vertical memory cells and the first peripheral circuits. A lower surface of the adhesive layer and an upper surface of the lower insulating interlayer may be in contact with each other.

公开(公告)号：US20180358370A1

公开(公告)日：2018-12-13

申请号：US15841762

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min HWANG ,  Joon-Sung Lim

IPC: H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11573 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a cell array region connected to a peripheral circuit region. The cell array region includes a plurality of electrode structures and a plurality of vertical structures on a body conductive layer. The plurality of electrode structures include a plurality of electrodes that are sequentially stacked on the body conductive layer. The plurality of vertical structures penetrate the electrode structures and are connected to the body conductive layer. The peripheral circuit region includes a peripheral transistor on a residual substrate. The residual substrate has a top surface higher than that of the body conductive layer.