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    Immediate feedback before or during programming
    23.
    发明授权
    Immediate feedback before or during programming 有权
    编程前或编程过程中的即时反馈

    公开(公告)号：US09583196B2

    公开(公告)日：2017-02-28

    申请号：US14607408

    申请日：2015-01-28

    Applicant: SanDisk Technologies LLC

    Inventor： Ariel Navon ,  Eran Sharon ,  Alexander Bazarsky ,  Noam Presman

    IPC: G11C11/34 ,  G11C16/10 ,  G11C16/34 ,  G11C16/12 ,  G11C29/02

    CPC classification number: G11C16/10 ,  G11C16/12 ,  G11C16/3427 ,  G11C16/3486 ,  G11C29/021 ,  G11C29/028

    Abstract: A system and method of programming user data into a memory cell includes receiving a first user data to be programmed in a memory controller, selecting a memory cell for programming the first user data and measuring at least one health characteristic of the selected memory cell. At least one programming parameter of the selected memory cell is adjusted and the first user data is programmed to the selected memory cell using the adjusted programming parameter corresponding to the selected memory cell.

    Abstract translation: 将用户数据编程到存储器单元中的系统和方法包括：接收要在存储器控制器中编程的第一用户数据，选择用于编程第一用户数据的存储单元并测量所选存储单元的至少一个健康特性。 调整所选存储单元的至少一个编程参数，并且使用对应于所选择的存储单元的经调整的编程参数将第一用户数据编程到所选存储单元。

    ECC in integrated memory assembly
    25.
    发明授权
    ECC in integrated memory assembly 有权

    公开(公告)号：US11482296B2

    公开(公告)日：2022-10-25

    申请号：US16891336

    申请日：2020-06-03

    Applicant: SanDisk Technologies LLC

    Inventor： Idan Alrod ,  Eran Sharon

    IPC: G11C29/42 ,  G11C29/18 ,  G11C29/44

    Abstract: Technology for error correcting data stored in memory dies is disclosed. Codewords, which may contain data bits and parity bits, are stored on a memory die. The memory die is bonded to a control die through bond pads that allow communication between the memory die and the control die. The codewords are decoded at the control die based on the parity bits. If the control die successfully decodes a codeword, the control die may send the data bits but not the parity bits to a memory controller. By not sending the parity bits to the memory controller, substantial bandwidth is saved. Also, substantial power may be saved. For example, the interface between the control die and the memory controller could be a high speed interface.

    Multi-type parity bit generation for encoding and decoding
    26.
    发明授权
    Multi-type parity bit generation for encoding and decoding 有权

    公开(公告)号：US10432232B2

    公开(公告)日：2019-10-01

    申请号：US15252753

    申请日：2016-08-31

    Applicant: SanDisk Technologies LLC

    Inventor： Ran Zamir ,  Alexander Bazarsky ,  Eran Sharon ,  Idan Alrod

    IPC: G06F11/10 ,  H03M13/35 ,  G06F3/06 ,  G11C29/52 ,  H03M13/11 ,  H03M13/27 ,  H03M13/29 ,  H03M13/00

    Abstract: A non-volatile memory system may be configured to generate a codeword with first-type parity bits and one or more second-type parity bits. If a storage location in which the codeword is to be stored includes one or more bad memory cells, the bit sequence of the codeword may be arranged so that at least some of the second-type parity bits are stored in the bad memory cells. During decoding, a first set of syndrome values may be determined for a first set of check nodes and a second set of syndrome values may be determined for a second set of check nodes. In some examples, a syndrome weight used for determining if convergence is achieved may be calculated using check nodes that are unassociated with the second-type parity bits.

    First read solution for memory
    27.
    发明授权
    First read solution for memory 有权

    公开(公告)号：US10372536B2

    公开(公告)日：2019-08-06

    申请号：US15921165

    申请日：2018-03-14

    Applicant: SanDisk Technologies LLC

    Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

    IPC: G11C16/28 ,  G06F11/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  G11C11/56 ,  G11C16/32

    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

    ECC decoder having adjustable parameters
    28.
    发明授权
    ECC decoder having adjustable parameters 有权

    公开(公告)号：US10250281B2

    公开(公告)日：2019-04-02

    申请号：US15395185

    申请日：2016-12-30

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Stella Achtenberg ,  Omer Fainzilber ,  Ariel Navon ,  Alexander Bazarsky ,  Eran Sharon

    IPC: G06F11/10 ,  H03M13/37 ,  H03M13/11 ,  G11C29/52

    Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.

    Data recovery in three dimensional non-volatile memory array after word line short
    30.
    发明授权
    Data recovery in three dimensional non-volatile memory array after word line short 有权

    公开(公告)号：US10133645B2

    公开(公告)日：2018-11-20

    申请号：US15414442

    申请日：2017-01-24

    Applicant: SanDisk Technologies LLC

    Inventor： Ofer Shapira ,  Idan Alrod ,  Eran Sharon

    IPC: G06F11/00 ,  G06F11/20 ,  G11C16/04 ,  G11C11/56 ,  G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G11C7/10

    Abstract: Data is programmed in a respective block of non-volatile three dimensional memory. The block contains a plurality of rows of subblocks, each row having S subblocks. Programming data in the respective block includes successively programming data in individual rows of the respective block. Programming data in each row is completed prior to programming data in a next row. Programming data in a row includes successively programming data in individual subblocks of the row, in a predefined order. The programming of data in each subblock is completed prior to programming data in a next subblock. While programming data in each individual subblock, a number of XOR signatures, sufficient in number to enable recovery from a short circuit that disables two or three word lines, are generated in volatile memory, and then copied to non-volatile memory prior to programming data in a next subblock in the respective block.

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