公开(公告)号：US09935143B2

公开(公告)日：2018-04-03

申请号：US15272093

申请日：2016-09-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Yukio Maehashi

IPC: H01L27/108 ,  H01L29/10 ,  H01L27/146 ,  H01L29/24 ,  H01L29/786 ,  H04N5/378

CPC classification number: H01L27/14616 ,  H01L27/14636 ,  H01L29/24 ,  H01L29/7869 ,  H04N5/378

Abstract: A small semiconductor device suitable for high-speed operation is provided. The semiconductor device includes a first circuit, a global bit line pair for writing, a global bit line pair for reading, and a local bit line pair. The first circuit includes second to fifth circuits. The second to fifth circuits are electrically connected to each other by the local bit line pair. The second circuit functions as a read/write selection switch. The third circuit functions as a working memory that stores 1-bit complementary data temporarily. The fourth circuit has a function of precharging the local bit line pair. The fifth circuit includes n (n is an integer of 2 or more) sixth circuits. The sixth circuits each have a function of retaining 1-bit complementary data written from the third circuit.

公开(公告)号：US09478704B2

公开(公告)日：2016-10-25

申请号：US13686366

申请日：2012-11-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuji Nishijima ,  Seiichi Yoneda ,  Takuro Ohmaru ,  Jun Koyama

IPC: H01L29/10 ,  H01L33/16 ,  G09G3/36 ,  H01L27/12 ,  G02F1/1362

CPC classification number: G09G3/3648 ,  G02F2001/136295 ,  G09G3/3614 ,  G09G3/3677 ,  G09G5/393 ,  G09G5/395 ,  G09G2300/0842 ,  G09G2310/0264 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2360/121 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869 ,  H01L33/16

Abstract: In the case where a still image is displayed on a pixel portion having a pixel, for example, a driver circuit for controlling writing of an image signal having image data to the pixel portion stops by stopping supply of power supply voltage to the driver circuit, and writing of an image signal to the pixel portion is stopped. After the driver circuit stops, supply of power supply voltage to a panel controller for controlling the operation of the driver circuit and an image memory for storing the image data is stopped, and supply of power supply voltage to a CPU for collectively controlling the operation of the panel controller, the image memory, and a power supply controller for controlling supply of power supply voltage to a variety of circuits in a semiconductor display device is stopped.

Abstract translation: 在静止图像显示在具有像素的像素部分的情况下，例如通过停止对驱动电路的电源电压的供给来停止将具有图像数据的图像信号写入到像素部分的驱动电路， 并且停止向像素部分写入图像信号。 在驱动器电路停止之后，停止向用于控制驱动器电路的操作的面板控制器的电源电压供给和用于存储图像数据的图像存储器，并且向CPU提供电源电压以集中地控制 停止面板控制器，图像存储器和用于控制对半导体显示装置中的各种电路的电源电压供给的电源控制器。

公开(公告)号：US09330759B2

公开(公告)日：2016-05-03

申请号：US14702817

申请日：2015-05-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru ,  Masami Endo

IPC: H03K3/356 ,  G11C14/00 ,  H01L29/24 ,  H01L27/108 ,  H01L49/02 ,  H01L29/786 ,  G11C11/24

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C11/24 ,  G11C14/0009 ,  G11C19/184 ,  H01L23/5226 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10897 ,  H01L28/20 ,  H01L28/40 ,  H01L29/24 ,  H01L29/26 ,  H01L29/7869 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

公开(公告)号：US09293193B2

公开(公告)日：2016-03-22

申请号：US14679110

申请日：2015-04-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/12 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/00 ,  G11C11/412

Abstract: To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.

公开(公告)号：US09165632B2

公开(公告)日：2015-10-20

申请号：US14160800

申请日：2014-01-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Takuro Ohmaru ,  Yasuyuki Takahashi

IPC: G11C11/22 ,  G11C11/24

CPC classification number: G11C11/22 ,  G11C11/24

Abstract: Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which the power supply voltage is not supplied; and a third circuit saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which the power supply voltage is not supplied. The third circuit includes a transistor in which a channel formation region is provided in an oxide semiconductor film and a capacitor to which a potential corresponding to the data is supplied through the transistor.

Abstract translation: 提供了具有降低的架空功率的存储器件。 一种存储装置，包括：第一电路，在供给电源电压的第一期间保持数据; 第二电路在第一时段中保存保留在第一电路中的数据，并且在不提供电源电压的第二周期内保留从第一电路保存的数据; 以及第三电路，在第二时段中保存保留在第二电路中的数据，并且在不提供电源电压的第三周期内保持从第二电路保存的数据。 第三电路包括其中沟道形成区域设置在氧化物半导体膜中的晶体管和通过晶体管提供对应于数据的电位的电容器。

公开(公告)号：US09153313B2

公开(公告)日：2015-10-06

申请号：US14223071

申请日：2014-03-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Takuro Ohmaru ,  Yasuyuki Takahashi

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/401 ,  G11C11/4074

CPC classification number: G11C11/4091 ,  G11C11/401 ,  G11C11/4074

Abstract: The first circuit has a function of retaining data in a first period during which a power supply voltage is supplied. The second circuit has functions of saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which application of the power supply voltage is stopped. The third circuit has functions of saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which application of the power supply voltage is stopped. The second circuit is capable of being written with the data for a shorter time than the third circuit. The third circuit is capable of maintaining the data for a longer time than the second circuit.

Abstract translation: 第一电路具有在提供电源电压的第一时段中保持数据的功能。 第二电路具有在第一时间段内保存保留在第一电路中的数据的功能，并且在停止施加电源电压的第二周期中保持从第一电路保存的数据。 第三电路具有在第二时段中保存保留在第二电路中的数据的功能，并且在停止施加电源电压的第三周期中保留从第二电路保存的数据。 第二电路能够以比第三电路更短的时间写入数据。 第三电路能够保持数据比第二电路更长的时间。

公开(公告)号：US09083327B2

公开(公告)日：2015-07-14

申请号：US13928555

申请日：2013-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru

IPC: G11C19/00 ,  H03K3/356 ,  H03K3/012 ,  H03K3/037 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/088 ,  G11C5/14 ,  G11C11/401 ,  H01L27/12

CPC classification number: H03K3/356008 ,  G11C5/148 ,  G11C11/401 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1225 ,  H03K3/012 ,  H03K3/0375

Abstract: A novel semiconductor device and a method of driving the semiconductor device. A (volatile) node in which data that is rewritten as appropriate by arithmetic processing is held and a node in which the data is stored are electrically connected to each other via a source and a drain of a transistor in which a channel is formed in an oxide semiconductor layer. Then, data and data obtained by inverting the data (inverted data) are stored before supply of power source voltage is stopped, and the two inputs (data) are compared after restart of supply of the power source voltage, so that data obtained by arithmetic processing just before the supply of the power source voltage is stopped is restored.

Abstract translation: 一种新型半导体器件和驱动该半导体器件的方法。 保持通过算术处理适当地重写的数据的数据被保存并且其中存储数据的节点经由其中在其中形成通道的晶体管的源极和漏极彼此电连接的（易失性）节点 氧化物半导体层。 然后，在供给电源电压停止之前存储反转数据（反转数据）而获得的数据和数据，并且在重新开始电源电压的重新开始之后比较两个输入（数据），使得通过算术获得的数据 恢复在电源电压供应停止之前的处理。

公开(公告)号：US09077333B2

公开(公告)日：2015-07-07

申请号：US14188734

申请日：2014-02-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru

IPC: H01L25/00 ,  H03K19/094 ,  H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0013 ,  H01L25/00 ,  H01L2924/0002 ,  H03K19/177 ,  H03K19/17744 ,  H01L2924/00

Abstract: A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a semiconductor device, first to fourth transistors are used as switches in a unit cell including an analog element, and the output of the unit cell switches between a conducting state, a non-conducting state, and a conducting state through the analog element by controlling the potential of a first node where the first transistor and the second transistor are connected and the potential of a second node where the third transistor and the fourth transistor are connected.

Abstract translation: 可编程模拟设备和模拟设备即使在供电电源中断并且功耗较低时也能保留数据。 在半导体器件中，第一至第四晶体管用作包括模拟元件的单元的开关，并且单元的输出通过模拟元件通过模拟元件在导通状态，非导通状态和导通状态之间切换， 控制第一晶体管和第二晶体管连接的第一节点的电位以及第三晶体管和第四晶体管连接的第二节点的电位。

公开(公告)号：US20140269014A1

公开(公告)日：2014-09-18

申请号：US14208714

申请日：2014-03-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru

IPC: G11C11/24 ,  G11C5/14

CPC classification number: G11C11/24 ,  G11C11/403 ,  G11C14/0054 ,  G11C2207/007 ,  H01L27/1156 ,  H01L27/1225

Abstract: A memory device with a novel structure that is suitable for a register file is provided. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit includes a first logic element and a second logic element each of which is configured to perform logic inversion, a selection circuit, a first switch, a second switch, and a third switch. The second memory circuit includes a first transistor in which a channel formation region is provided in an oxide semiconductor film, a second transistor, and a capacitor to which a potential is supplied through the first transistor.

Abstract translation: 提供了一种适用于寄存器文件的具有新颖结构的存储器件。 存储器件包括第一存储器电路和第二存储器电路。 第一存储器电路包括第一逻辑元件和第二逻辑元件，每个逻辑元件被配置为执行逻辑反转，选择电路，第一开关，第二开关和第三开关。 第二存储电路包括第一晶体管，其中沟道形成区域设置在氧化物半导体膜，第二晶体管和电容器中，通过第一晶体管提供电位。

公开(公告)号：US20130221344A1

公开(公告)日：2013-08-29

申请号：US13768743

申请日：2013-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Shuhei Nagatsuka

IPC: H01L29/786 ,  H01L27/088

CPC classification number: H01L29/786 ,  H01L27/088 ,  H01L27/1225 ,  H03K3/0315 ,  H03K19/0013 ,  H03K19/20 ,  H03K2005/00032 ,  H03K2005/00195 ,  H03K2217/0018

Abstract: To provide a semiconductor device including an inverter circuit whose driving frequency is increased by control of the threshold voltage of a transistor or a semiconductor device including an inveter circuit with low power consumption. An inverter circuit includes a first transistor and a second transistor each including a semiconductor film in which a channel is formed, a pair of gate electrodes between which the semiconductor film is placed, and source and drain electrodes in contact with the semiconductor film. Controlling potentials applied to the pair of gate electrodes makes the first transistor have normally-on characteristics and the second transistor have normally-off characteristics. Thus, the driving frequency of the inverter circuit is increased.

Abstract translation: 为了提供一种半导体器件，其包括通过控制晶体管的阈值电压或包括具有低功耗的入侵电路的半导体器件来驱动驱动频率的逆变器电路。 逆变器电路包括第一晶体管和第二晶体管，每个晶体管和第二晶体管都包括其中形成沟道的半导体膜，放置半导体膜的一对栅极电极和与半导体膜接触的源极和漏极。 施加到一对栅电极的控制电位使得第一晶体管具有常开特性，而第二晶体管具有常关特性。 因此，逆变器电路的驱动频率增加。