公开(公告)号：US20170162700A1

公开(公告)日：2017-06-08

申请号：US15432977

申请日：2017-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masahiro TAKAHASHI ,  Hideyuki KISHIDA ,  Akiharu MIYANAGA ,  Junpei SUGAO ,  Hideki UOCHI ,  Yasuo NAKAMURA

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/24 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/324 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76838 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

公开(公告)号：US20160268360A1

公开(公告)日：2016-09-15

申请号：US15163296

申请日：2016-05-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hisao IKEDA ,  Hideki UOCHI

IPC: H01L27/32 ,  H01L51/52

CPC classification number: H01L27/3262 ,  G06F2203/04102 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1266 ,  H01L27/322 ,  H01L27/323 ,  H01L27/3248 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/78633 ,  H01L29/7869 ,  H01L51/5246 ,  H01L2251/5338

Abstract: A non-breakable display device, electronic appliance, or lighting device is provided. A bendable display device in which a first flexible substrate and a second flexible substrate provided with transistors overlap each other with a bonding layer therebetween is fabricated. The display device is bent so that the first substrate is positioned on the inner side (the valley side) and the second substrate is positioned on the outer side (the mountain side).

公开(公告)号：US20160254257A1

公开(公告)日：2016-09-01

申请号：US15150744

申请日：2016-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: H01L27/02 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/1339 ,  G02F1/1333 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L27/0266 ,  G02F1/133305 ,  G02F1/1339 ,  G02F1/13394 ,  G02F1/134309 ,  G02F1/13624 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A protective circuit includes a non-linear element, which further includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a conductive layer and a second oxide semiconductor layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with side face portions of the gate insulating layer and the conductive layer of the first wiring layer and the second wiring layer and a side face portion and a top face portion of the second oxide semiconductor layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.

Abstract translation: 保护电路包括非线性元件，其还包括栅电极，覆盖栅电极的栅极绝缘层，一对第一和第二布线层，其端部与栅极绝缘层上的栅极重叠，并且其中 堆叠导电层和第二氧化物半导体层，以及与至少栅电极重叠并与栅极绝缘层和第一布线层的导电层的侧面部分接触的第一氧化物半导体层和 第二布线层和第二氧化物半导体层的侧面部分和顶面部分。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。

公开(公告)号：US20150296162A1

公开(公告)日：2015-10-15

申请号：US14679172

申请日：2015-04-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Hideki UOCHI

IPC: H04N5/374 ,  H01L27/146 ,  H01L31/105 ,  H01L29/786

CPC classification number: H04N5/3741 ,  H01L27/1225 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14687 ,  H01L29/7869 ,  H01L31/105

Abstract: To provide a solid-state imaging device with short image-capturing duration. A first photodiode in a pixel in an n-th row and an m-th column is connected to a second photodiode in a pixel in an (n+1)-th row and the m-th column through a transistor. The first photodiode and the second photodiode receive light concurrently, the potential in accordance with the amount of received light is held in a pixel in the n-th row and the m-th column, and the potential in accordance with the amount of received light is held in a pixel in the (n+1)-th row and the m-th column without performing a reset operation. Then, each potential is read out. Under a large amount of light, either the first photodiode or the second photodiode is used.

Abstract translation: 提供具有短图像捕获持续时间的固态成像装置。 第n行和第m列的像素中的第一光电二极管通过晶体管连接到第（n + 1）行和第m列的像素中的第二光电二极管。 第一光电二极管和第二光电二极管同时接收光，根据接收光量的电位被保持在第n行和第m列的像素中，并且根据接收光量的电位 被保持在第（n + 1）行和第m列的像素中，而不执行复位操作。 然后，读出每个电位。 在大量的光下，使用第一光电二极管或第二光电二极管。

公开(公告)号：US20250040116A1

公开(公告)日：2025-01-30

申请号：US18780752

申请日：2024-07-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takanori MATSUZAKI ,  Yuto YAKUBO ,  Yuki OKAMOTO ,  Hideki UOCHI

IPC: H10B12/00

Abstract: A novel memory device is provided. A plurality of memory cells each including two vertical transistors are connected in series. One of the two transistors functions as a transistor for writing data, and the other functions as a transistor for reading the data that has been written to the memory cell. Data written to the memory cell is retained in a gate of the reading transistor. A transistor with low off-state current is used as the writing transistor.

公开(公告)号：US20240155869A1

公开(公告)日：2024-05-09

申请号：US18279942

申请日：2022-03-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shingo EGUCHI ,  Hideki UOCHI

IPC: H10K59/12 ,  H10K71/16 ,  H10K71/60

CPC classification number: H10K59/1201 ,  H10K71/166 ,  H10K71/60

Abstract: A method for fabricating a novel display device is provided. The method for fabricating the display device includes a step of forming an anode, a first EL layer, a first cathode, and a first layer in this order; a step of forming a first resist mask over the first layer; a step of selectively removing parts of the anode, the first EL layer, the first cathode, and the first layer; a step of removing part of the first resist mask; a step of selectively removing other parts of the first EL layer, the first cathode, and the first layer; and a step of removing the first resist mask. The first resist mask is formed using a multi-tone mask.

公开(公告)号：US20230112113A1

公开(公告)日：2023-04-13

申请号：US18081109

申请日：2022-12-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiaki OIKAWA ,  Atsushi MIYAGUCHI ,  Hideki UOCHI

IPC: G11C11/16 ,  G11C11/419 ,  H01L29/786

Abstract: A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.

公开(公告)号：US20220262438A1

公开(公告)日：2022-08-18

申请号：US17629801

申请日：2020-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Tatsuya ONUKI ,  Yuki OKAMOTO ,  Hideki UOCHI ,  Satoru OKAMOTO

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/786

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

公开(公告)号：US20210272614A1

公开(公告)日：2021-09-02

申请号：US17326441

申请日：2021-05-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiaki OIKAWA ,  Atsushi MIYAGUCHI ,  Hideki UOCHI

IPC: G11C11/16 ,  G11C11/419 ,  H01L27/22 ,  H01L29/786 ,  H01L43/02

Abstract: A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.

公开(公告)号：US20210257020A1

公开(公告)日：2021-08-19

申请号：US16972696

申请日：2019-06-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Toshihiko SAITO ,  Hideki UOCHI ,  Shunpei YAMAZAKI

IPC: G11C11/419 ,  H01L29/786 ,  H01L29/04 ,  G11C11/409

Abstract: A novel memory device is provided. The memory device includes a plurality of memory cells, and one memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Data written through the first transistor is retained at the node SN. When an OS transistor is used as the first transistor, formation of a storage capacitor is not needed. A region with a low dielectric constant is provided outside the memory cell, whereby noise from the outside is reduced and stable operation is achieved.