公开(公告)号：US20190146674A1

公开(公告)日：2019-05-16

申请号：US16224623

申请日：2018-12-18

Applicant: SK hynix Inc.

Inventor： Do-Sun HONG ,  Donggun KIM ,  Yong Ju KIM ,  Sang Gu JO

IPC: G06F3/06 ,  G06F11/07 ,  G06F12/02 ,  G11C13/00

Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write accesses for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

公开(公告)号：US20180156870A1

公开(公告)日：2018-06-07

申请号：US15650403

申请日：2017-07-14

Applicant: SK hynix Inc. ,  KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

Inventor： Chul Woo KIM ,  Dong Yoon KIM ,  In Hwa JUNG ,  Yong Ju KIM

IPC: G01R31/319 ,  G01R31/28 ,  G06F11/22 ,  G01R31/3167

CPC classification number: G01R31/31905 ,  G01R31/286 ,  G01R31/2879 ,  G01R31/3167 ,  G01R31/31922 ,  G01R31/31926 ,  G06F11/22

Abstract: A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.

公开(公告)号：US20180081545A1

公开(公告)日：2018-03-22

申请号：US15434784

申请日：2017-02-16

Applicant: SK hynix Inc.

Inventor： Do-Sun HONG ,  Donggun KIM ,  Yong Ju KIM ,  Sang Gu JO

IPC: G06F3/06 ,  G11C13/00 ,  G06F11/07 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0793 ,  G06F12/0246 ,  G06F2212/202 ,  G06F2212/657 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069

Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write access for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

公开(公告)号：US20180052732A1

公开(公告)日：2018-02-22

申请号：US15469047

申请日：2017-03-24

Applicant: SK hynix Inc.

Inventor： Sang Gu JO ,  Jung Hyun KWON ,  Donggun KIM ,  Yong Ju KIM ,  Sungeun LEE ,  Jae Sun LEE ,  JINGZHE XU ,  Do-Sun HONG

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G11C29/52 ,  G11C2029/0401

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a transmission command and a transmission address, being inputted with and outputting transmission data, and generating an error flag signal when an error bit is included in the transmission data inputted in a read operation. The semiconductor system may include a second semiconductor device configured for storing the transmission address in a lookup table circuit when the error flag signal is enabled, and comparing the transmission address and a storage address stored in the lookup table circuit when the read operation is performed based on the transmission command and outputting the transmission data from the lookup table circuit.

公开(公告)号：US20160292090A1

公开(公告)日：2016-10-06

申请号：US14725003

申请日：2015-05-29

Applicant: SK hynix Inc.

Inventor： Yong Ju KIM ,  Sang Gu JO ,  Jae Sun LEE

IPC: G06F13/10 ,  G06F13/12

CPC classification number: G06F13/102 ,  G06F13/12

Abstract: A data processing system includes a plurality of peripheral devices in which device identification information and group identification information are stored, and a controller. The peripheral devices of the same species device group have the same group identification information, and peripheral devices from different peripheral device groups have different group identification information. The controller controls peripheral devices of the same species device group to perform the same operation.

Abstract translation: 数据处理系统包括存储设备识别信息和组识别信息的多个外围设备和控制器。 同一种类设备组的外围设备具有相同的组识别信息，来自不同外设设备组的外围设备具有不同的组识别信息。 控制器控制同一物种设备组的外围设备执行相同的操作。

公开(公告)号：US20150076703A1

公开(公告)日：2015-03-19

申请号：US14550445

申请日：2014-11-21

Applicant: SK hynix Inc.

Inventor： Chang Kun PARK ,  Seong Hwi SONG ,  Yong Ju KIM ,  Sung Woo HAN ,  Hee Woong SONG ,  Ic Su OH ,  Hyung Soo KIM ,  Tae Jin HWANG ,  Hae Rang CHOI ,  Ji Wang LEE ,  Jae Min JANG

IPC: H01L23/00 ,  H01L27/105

CPC classification number: H01L24/06 ,  H01L23/5286 ,  H01L24/09 ,  H01L27/1052 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06515 ,  H01L2224/091 ,  H01L2224/09515 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/30101 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

公开(公告)号：US20140010029A1

公开(公告)日：2014-01-09

申请号：US13797574

申请日：2013-03-12

Applicant: University Of Seoul Industry Cooperation Foundation ,  SK HYNIX INC.

Inventor： Jong Gon JUNG ,  Yong Sam MOON ,  Yong Ju KIM ,  Jong Ho JUNG

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C2207/2272

Abstract: A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.

Abstract translation: 延迟控制电路包括：时钟延迟，被配置为输出通过以相同间隔串行延迟输入时钟信号而获得的多个串行延迟信号;偏差信息生成单元，被配置为基于延迟值生成偏差信息， 时钟信号经历芯片，等待时间信息，时钟选择器，被配置为基于多个串行延迟信号和偏差信息输出多个时钟选择信号;命令信号处理单元，被配置为基于 输入命令信号，并通过可变地延迟读取信号来输出可变延迟复制信号;以及等待时间移位器，配置为通过将多个时钟选择信号与可变延迟复制信号组合来输出等待时间信号。

公开(公告)号：US20140003161A1

公开(公告)日：2014-01-02

申请号：US13720319

申请日：2012-12-19

Applicant: SK HYNIX INC.

Inventor： Jong Ho SON ,  Yong Ju KIM

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G01K7/425 ,  G11C11/41 ,  G11C29/50016 ,  G11C29/56 ,  G11C29/56012 ,  G11C2029/5002

Abstract: A test circuit of a semiconductor apparatus includes a test temperature information generation section, an erroneous operation prevention unit, and a refresh cycle adjustment unit. The test temperature information generation section outputs test temperature information having a plurality of bits in a test operation mode, and irregularly changes logic values of the plurality of bits and transition time points of the logic values. The erroneous operation prevention unit generates a temperature compensation signal in response to the test temperature information. The refresh cycle adjustment unit changes a cycle of a reference refresh signal in response to the temperature compensation signal, and generates a refresh signal.

Abstract translation: 半导体装置的测试电路包括测试温度信息产生部分，错误操作防止单元和刷新周期调节单元。 测试温度信息生成部分在测试操作模式下输出具有多个位的测试温度信息，并且不规则地改变逻辑值的多个位的逻辑值和转换时间点。 错误操作防止单元根据测试温度信息生成温度补偿信号。 刷新周期调整单元响应于温度补偿信号改变参考刷新信号的周期，并产生刷新信号。