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    FLASH MEMORY DEVICE AND COMPUTING DEVICE INCLUDING FLASH MEMORY CELLS
    21.
    发明申请
    FLASH MEMORY DEVICE AND COMPUTING DEVICE INCLUDING FLASH MEMORY CELLS 有权

    公开(公告)号：US20220180917A1

    公开(公告)日：2022-06-09

    申请号：US17682100

    申请日：2022-02-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chanho KIM ,  Daeseok BYEON ,  Hyunsurk RYU

    IPC: G11C11/4093 ,  G11C11/4094 ,  G11C5/06 ,  G11C11/408 ,  G11C16/04 ,  G11C16/08

    Abstract: Flash memory device includes: first pads to be bonded to external semiconductor chip, to receive at least one of command, address and control signals; second pads to be bonded to external semiconductor chip; memory cell array including memory cells; a row decoder block connected to memory cell array through word lines, to select one of word lines based on address provided to row decoder block; a buffer block to store command and address and provide address to row decoder block; a page buffer block connected to memory cell array through bit lines, connected to second pads through data lines without passing through buffer block, and configured to exchange data signals with external semiconductor chip through data lines and second pads; and a control logic block configured to receive command from buffer block, to receive control signals from external semiconductor chip, and to control row decoder block and page buffer block.

    MEMORY DEVICE
    22.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20220102335A1

    公开(公告)日：2022-03-31

    申请号：US17545522

    申请日：2021-12-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jooyong PARK ,  Chanho KIM ,  Daeseok BYEON

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00

    Abstract: A memory device includes first and second chips. The first chip includes a memory cell array disposed on a first substrate, and first metal pads on a first uppermost metal layer of the first chip. The second chip includes peripheral circuits disposed on a second substrate, and second metal pads on a second uppermost metal layer of the second chip, the peripheral circuits operating the memory cell array. A first metal pad and a second metal pad are connected in a first area, the first metal pads being connected to the memory cell array and the second metal pad being connected to the peripheral circuits. A further first metal pad and a further second metal pad are connected in a second area, the further first metal pad being not connected to the memory cell array and the further second metal pad being connected to the peripheral circuits.

    NONVOLATILE MEMORY DEVICE
    23.
    发明申请
    NONVOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20220075565A1

    公开(公告)日：2022-03-10

    申请号：US17455037

    申请日：2021-11-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghyuk CHOI ,  Jaeduk YU ,  Sangwan NAM ,  Sangwon PARK ,  Daeseok BYEON ,  Bongsoon LIM

    IPC: G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

    Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

    VERTICAL CAPACITOR STRUCTURE AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME
    24.
    发明申请
    VERTICAL CAPACITOR STRUCTURE AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20200321349A1

    公开(公告)日：2020-10-08

    申请号：US16662073

    申请日：2019-10-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehong KWON ,  Chanho KIM ,  Daeseok BYEON ,  Pansuk KWAK ,  Chiweon YOON

    IPC: H01L27/11573 ,  H01L27/11582 ,  H01L29/94 ,  H01L29/78

    Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

    THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING PERIPHERAL CIRCUITS
    27.
    发明公开
    THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE INCLUDING PERIPHERAL CIRCUITS 审中-公开

    公开(公告)号：US20230255037A1

    公开(公告)日：2023-08-10

    申请号：US18095147

    申请日：2023-01-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beakhyung CHO ,  Daeseok BYEON

    IPC: H10B80/00

    CPC classification number: H10B80/00

    Abstract: In some embodiments, a non-volatile memory device includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes gate electrodes, channel structures, a plurality of cell contact plugs, a linear metal pattern, and a plurality of upper bonding pads. The second semiconductor chip includes a plurality of lower bonding pads, a first peripheral circuit element overlapping the channel structures, a second peripheral circuit element overlapping the plurality of cell contact plugs, and a third peripheral circuit element overlapping the plurality of cell contact plugs. The peripheral circuit elements are coupled to corresponding cell contact plugs. Widths in the first direction of the second upper bonding pad and the third upper bonding pad are different from each other, and widths in the first direction of the second lower bonding pad and the third lower bonding pad are different from each other.

    INTEGRATED CIRCUIT INCLUDING POWER GATING CIRCUIT
    29.
    发明申请
    INTEGRATED CIRCUIT INCLUDING POWER GATING CIRCUIT 有权

    公开(公告)号：US20230073878A1

    公开(公告)日：2023-03-09

    申请号：US17886194

    申请日：2022-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changyeon YU ,  Pansuk KWAK ,  Daeseok BYEON

    IPC: H03K19/00 ,  H03K19/003 ,  G06F1/26 ,  H03K3/027 ,  H03K17/687

    Abstract: An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.

    MEMORY DEVICE HAVING PHYSICAL UNCLONABLE FUNCTION AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    30.
    发明申请
    MEMORY DEVICE HAVING PHYSICAL UNCLONABLE FUNCTION AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 有权

    公开(公告)号：US20220399056A1

    公开(公告)日：2022-12-15

    申请号：US17569786

    申请日：2022-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jooyong PARK ,  Pansuk KWAK ,  Daeseok BYEON

    IPC: G11C13/00 ,  G11C5/06

    Abstract: Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

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