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    Stacked semiconductor package
    22.
    发明授权
    Stacked semiconductor package 有权

    公开(公告)号：US11508685B2

    公开(公告)日：2022-11-22

    申请号：US16992895

    申请日：2020-08-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jihwan Suh ,  Un-Byoung Kang ,  Taehun Kim ,  Hyuekjae Lee ,  Jihwan Hwang ,  Sang Cheon Park

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

    Semiconductor package
    27.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12261164B2

    公开(公告)日：2025-03-25

    申请号：US18480310

    申请日：2023-10-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang Cheon Park ,  Dae-Woo Kim ,  Taehun Kim ,  Hyuekjae Lee

    IPC: H01L23/495 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/18

    Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.

    SEMICONDUCTOR PACKAGE
    29.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240096831A1

    公开(公告)日：2024-03-21

    申请号：US18455943

    申请日：2023-08-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Enbin Jo ,  Hyungchul Shin ,  Wonil Lee ,  Hyuekjae Lee ,  Gwangjae Jeon

    IPC: H01L23/00 ,  H01L25/065

    CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L24/16 ,  H01L2224/0801 ,  H01L2224/08058 ,  H01L2224/08146 ,  H01L2224/16227 ,  H01L2225/06541 ,  H01L2924/37

    Abstract: A semiconductor package includes: a first semiconductor chip including a first pad on a first substrate, and a first insulating layer at least partially surrounding the first pad; and a second semiconductor chip including a second pad below a second substrate and contacting the first pad, and a second insulating layer at least partially surrounding the second pad and contacting the first insulating layer. The first pad includes a first surface contacting the second pad and a second surface opposite the first surface, and an inclined side surface between the first surface and the second surface. The inclined side surface includes a first side surface and a second side surface, facing each other and inclined at a first obtuse angle and a second obtuse angle with respect to the second surface, respectively. Each of the first and second obtuse angles is about 100° to about 130°.

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