公开(公告)号：US20250089352A1

公开(公告)日：2025-03-13

申请号：US18434041

申请日：2024-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Byeong Hee Son

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor includes a substrate, first and second active patterns that are on the substrate and extend in a first horizontal direction, a first gate electrode that is on the first active pattern and extends in a second horizontal direction, a second gate electrode that is on the second active pattern and extends in the second horizontal direction, an active cut trench that extends in the second horizontal direction and is between the first gate electrode and the second gate electrode, an active cut including a first layer and a second layer on the first layer, a first source/drain region that is between the first gate electrode and the active cut and is on the first active pattern, and a first source/drain contact that is on the first source/drain region, where at least a part of the first source/drain contact overlaps the first layer in a vertical direction.

公开(公告)号：US12183800B2

公开(公告)日：2024-12-31

申请号：US18449734

申请日：2023-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dong Won Kim ,  Woo Seok Park ,  Keun Hwi Cho ,  Sung Gi Hur

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786

Abstract: Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

公开(公告)号：US20240421189A1

公开(公告)日：2024-12-19

申请号：US18596179

申请日：2024-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Jin Park ,  Myung Gil Kang ,  Dong Won Kim ,  Chang Woo Noh ,  Yu Jin Jeon

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor devices. An example semiconductor device includes a substrate including first and second regions, a first bridge pattern extending in a first direction on the first region, a first gate structure extending in a second direction intersecting the first direction, first epitaxial patterns connected to the first bridge pattern on side surfaces of the first gate structure, first inner spacers interposed between the substrate and the first bridge pattern and between the first gate structure and the first epitaxial patterns, a second bridge pattern extending in the first direction on the second region, a second gate structure extending in the second direction, second epitaxial patterns connected to the second bridge pattern on side surfaces of the second gate structure, and second inner spacers interposed between the substrate and the second bridge pattern and between the second gate structure and the second epitaxial patterns.

公开(公告)号：US20240405073A1

公开(公告)日：2024-12-05

申请号：US18538290

申请日：2023-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyumin Yoo ,  Myung Gil Kang ,  Dongwon Kim ,  Jongsu Kim ,  Changwoo Noh ,  Beomjin Park ,  Soojin Jeong ,  Woosuk Choi

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device is provided including an active pattern disposed on a substrate, a source/drain pattern on the active pattern, a channel pattern configured to electrically connect the source/drain patterns and including stacked semiconductor patterns spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, a gate pattern configured to cross between the source/drain patterns in a second direction parallel to the upper surface of the substrate, on the channel pattern, and to have a main gate portion and sub-gate portions, and inner gate spacers between the sub-gate portions and the source/drain pattern. A first distance between adjacent source/drain patterns along a given one of the sub-gate portions in the second direction is greater than a second distance between adjacent source/drain patterns passing through the semiconductor patterns in the second direction.

公开(公告)号：US20240186392A1

公开(公告)日：2024-06-06

申请号：US18062116

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin PARK ,  Myung Gil Kang ,  Dong Won Kim ,  Keun Hwi Cho

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/775

Abstract: A semiconductor device including a substrate, a first and second active pattern extending in a first horizontal direction on the substrate, the second active pattern apart from the first active pattern in the first horizontal direction, first nanosheets apart from each other in a vertical direction on the first active pattern, second nanosheets apart from each other in the vertical direction on the first and second active patterns, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the first active pattern and surrounding the first nanosheets, a source/drain region between the first and second nanosheets, an active cut penetrating the second nanosheets in the vertical direction, extending to the substrate, and separating the first and second active patterns, and a sacrificial layer between the source/drain region and the active cut, in contact with the active cut, and including silicon germanium may be provided.

公开(公告)号：US11990534B2

公开(公告)日：2024-05-21

申请号：US17886612

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Gil Kang ,  Dongwon Kim ,  Minyi Kim ,  Keun Hwi Cho

IPC: H01L29/732 ,  H01L21/8228 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/732 ,  H01L21/82285 ,  H01L21/823821 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/735

Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.

公开(公告)号：US11843000B2

公开(公告)日：2023-12-12

申请号：US17336785

申请日：2021-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin Park ,  Myung Gil Kang ,  Dong Won Kim ,  Keun Hwi Cho

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/02603 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOI substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.

公开(公告)号：US20230290783A1

公开(公告)日：2023-09-14

申请号：US18059639

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongsoon Kong ,  Myung Gil Kang ,  Sanghoon Baek

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11831 ,  H01L2027/11853 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including an N-stack cell, a buffer cell and an M-stack cell that are on the substrate, the buffer cell being between the N-stack and M-stack cells, an active pattern extending from the N-stack cell to the M-stack cell via the buffer cell, an N-stack channel pattern on the active pattern of the N-stack cell, an M-stack channel pattern on the active pattern of the M-stack cell, a dummy channel pattern on the active pattern of the buffer cell, an N-stack epitaxial pattern between the N-stack channel pattern and the dummy channel pattern, and an M-stack epitaxial pattern between the M-stack channel pattern and the dummy channel pattern. The N-stack channel pattern includes stacked N semiconductor patterns. The M-stack channel pattern includes stacked M semiconductor patterns. Each of N and M is an integer number of 2 or more, and M is greater than N.

公开(公告)号：US09870957B2

公开(公告)日：2018-01-16

申请号：US15290456

申请日：2016-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo Yeon Jeong ,  Myung Gil Kang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/417 ,  H01L29/49 ,  H01L23/535 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785

Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode.

公开(公告)号：US20240363625A1

公开(公告)日：2024-10-31

申请号：US18422471

申请日：2024-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin Park ,  Myung Gil Kang ,  Dong Won Kim ,  Young Gwon Kim ,  Soo Jin Jeong

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor includes a substrate having a first conductivity type; a well region having a second conductivity type in the substrate; an impurity implantation region having the first conductivity type in the well region; an element separation pattern in the substrate; a first fin pattern defined by the element separation pattern in the impurity implantation region; a second fin pattern defined by the element separation pattern in the well region; and a third fin pattern defined by the element separation pattern in the substrate, wherein the first fin pattern is a single fin, and an entirety of a lower boundary of the impurity implantation region is in contact with the well region.