公开(公告)号：US11538798B2

公开(公告)日：2022-12-27

申请号：US17184978

申请日：2021-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong Hwang ,  Kyoung Lim Suk ,  Seokhyun Lee ,  Jaegwon Jang

IPC: H01L25/10 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.

公开(公告)号：US11456241B2

公开(公告)日：2022-09-27

申请号：US16884212

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Jongyoun Kim ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

公开(公告)号：US20220285328A1

公开(公告)日：2022-09-08

申请号：US17648424

申请日：2022-01-20

Applicant: Samsung Electronics Co., LTD

Inventor： DONGKYU KIM ,  Daeho Lee ,  Seokhyun Lee ,  Minjung Kim ,  Taewon Yoo

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a lower semiconductor chip disposed on a lower redistribution substrate, lower solder patterns disposed between the lower redistribution substrate and the lower semiconductor chip, conductive structures disposed on the lower redistribution substrate, a lower molding layer disposed on the lower redistribution substrate and covering a top surface of the lower semiconductor chip, an upper redistribution substrate disposed on the lower molding layer and electrically connected to the conductive structures, an upper semiconductor chip disposed on the upper redistribution substrate, upper solder patterns disposed between the upper redistribution substrate and the upper semiconductor chip, and an upper molding layer disposed on the upper redistribution substrate and covering a sidewall of the upper semiconductor chip. The number of the conductive structures is greater than that of chip pads of the upper semiconductor chip.

公开(公告)号：US20220130685A1

公开(公告)日：2022-04-28

申请号：US17331751

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US20210407940A1

公开(公告)日：2021-12-30

申请号：US17474614

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Jungho Park ,  Seokhyun Lee ,  Yeonho Jang ,  Jaegwon Jang

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

公开(公告)号：US10950539B2

公开(公告)日：2021-03-16

申请号：US16351709

申请日：2019-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun Kim ,  Seokhyun Lee ,  Minjun Bae

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A redistribution subtrate, a method of fabricating the same, and a semiconductor package are provided. The method including forming a first conductive pattern; forming a first photosensitive layer on the first conductive pattern, the first photosensitive layer having a first through hole exposing a first portion of the first conductive pattern; forming a first via in the first through hole; removing the first photosensitive layer; forming a first dielectric layer that encapsulates the first conductive pattern and the first via, the first dielectric layer exposing a top surface of the first via; and forming a second conductive pattern on the top surface of the first via.

公开(公告)号：US10319650B2

公开(公告)日：2019-06-11

申请号：US15603859

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Seokhyun Lee

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/31 ,  H01L21/48 ,  H01L25/10 ,  H01L21/66 ,  H01L23/538

Abstract: A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.

公开(公告)号：US09640513B2

公开(公告)日：2017-05-02

申请号：US14682113

申请日：2015-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Chul-Yong Jang ,  Jongho Lee

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10 ,  H01L23/13 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/29036 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.

公开(公告)号：US12293989B2

公开(公告)日：2025-05-06

申请号：US17680857

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Kim ,  Dongkyu Kim ,  Jongyoun Kim ,  Seokhyun Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package includes a first redistribution substrate, a lower semiconductor chip on the first redistribution substrate and a through via therein, a first lower conductive structure and a second lower conductive structure that are on the first redistribution substrate and are laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and the second lower conductive structure and coupled to the through via and the second lower conductive structure, and an upper conductive structure on the first lower conductive structure. A width of the second lower conductive structure is greater than a width of the through via.

公开(公告)号：US20240105689A1

公开(公告)日：2024-03-28

申请号：US18212514

申请日：2023-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhyun Lee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor package includes: a lower redistribution wiring layer having: a first chip mounting region; a peripheral region, and lower redistribution wirings; a logic semiconductor chip mounted in the first chip mounting region, the logic semiconductor chip having a plurality of first through electrodes that are electrically connected to at least some of the lower redistribution wirings; a first sealing member covering the logic semiconductor chip, a plurality of conductive connectors penetrating the first sealing member in the peripheral region; an upper redistribution wiring layer provided on the first seal and having upper redistribution wirings that are electrically connected to the plurality of conductive connectors, the upper redistribution wiring layer having at least one second chip mounting region that overlaps at least a portion of the first chip mounting region; and at least one memory semiconductor chip mounted in the second chip mounting region using first and second conductive bumps.