公开(公告)号：US09640513B2

公开(公告)日：2017-05-02

申请号：US14682113

申请日：2015-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Chul-Yong Jang ,  Jongho Lee

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L25/10 ,  H01L23/13 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/29036 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.

公开(公告)号：US09364914B2

公开(公告)日：2016-06-14

申请号：US14471327

申请日：2014-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhyun Lee ,  Jaegwon Jang ,  Chul-Yong Jang

IPC: H01L23/02 ,  B23K3/06 ,  B23K1/00 ,  B23K1/20 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: B23K3/0623 ,  B23K1/0016 ,  B23K1/203 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/45099

Abstract: Provided are apparatuses configured to attach a solder ball, methods of attaching a solder ball, and methods of fabricating a semiconductor package including the same. An apparatus configured to attach a solder ball includes a chuck configured to receive a package substrate on which solder balls are provided; a shielding mask configured to shield the package substrate and including holes configured to expose the solder balls; and a heater configured to melt the solder balls exposed through the holes.

Abstract translation: 提供了构造成附接焊球的装置，附接焊球的方法，以及制造包括该焊球的半导体封装的方法。 构造成附接焊球的装置包括：卡盘，其配置成接收其上设置有焊球的封装基板; 屏蔽掩模，被配置为屏蔽所述封装基板并且包括被配置为暴露所述焊球的孔; 以及被配置为熔化通过孔暴露的焊球的加热器。

公开(公告)号：US09281235B2

公开(公告)日：2016-03-08

申请号：US14613154

申请日：2015-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-lyong Kim ,  Taehoon Kim ,  Jongho Lee ,  Chul-Yong Jang

IPC: H01L21/768 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L21/76802 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24146 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.